| Message ID | 1445521485-2029-4-git-send-email-jarkko.nikula@linux.intel.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 0e8972187971ac6c29a9e5899fa6c555c739237c |
| Headers | show |
Jarkko Nikula <jarkko.nikula@linux.intel.com> writes: > Upcoming Intel platforms use LPSS SPI_CS_CONTROL register bits 15:12 for > configuring the chip select polarities. Touch only chip select SW mode and > state bits when enabling the software chip select control in order to not > clear any other bits in the register. > > Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Cheers.
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 48fdcb6a7f79..615f6c57a090 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -249,7 +249,9 @@ static void lpss_ssp_setup(struct driver_data *drv_data) drv_data->lpss_base = drv_data->ioaddr + config->offset; /* Enable software chip select control */ - value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; + value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); + value &= ~(SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH); + value |= SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); /* Enable multiblock DMA transfers */
Upcoming Intel platforms use LPSS SPI_CS_CONTROL register bits 15:12 for configuring the chip select polarities. Touch only chip select SW mode and state bits when enabling the software chip select control in order to not clear any other bits in the register. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> --- drivers/spi/spi-pxa2xx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)