From patchwork Wed Oct 28 13:13:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jarkko Nikula X-Patchwork-Id: 7510541 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 667CB9F327 for ; Wed, 28 Oct 2015 13:14:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8B176206CE for ; Wed, 28 Oct 2015 13:14:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E0461207F9 for ; Wed, 28 Oct 2015 13:14:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965524AbbJ1NON (ORCPT ); Wed, 28 Oct 2015 09:14:13 -0400 Received: from mga14.intel.com ([192.55.52.115]:19351 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751123AbbJ1NOL (ORCPT ); Wed, 28 Oct 2015 09:14:11 -0400 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP; 28 Oct 2015 06:13:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,210,1444719600"; d="scan'208";a="805489138" Received: from mylly.fi.intel.com (HELO mylly.fi.intel.com.) ([10.237.72.53]) by orsmga001.jf.intel.com with ESMTP; 28 Oct 2015 06:13:45 -0700 From: Jarkko Nikula To: linux-spi@vger.kernel.org Cc: Mark Brown , Daniel Mack , Haojian Zhuang , Robert Jarzmik , Jarkko Nikula Subject: [PATCH 1/5] spi: pxa2xx: Use LPSS prefix for defines that are Intel LPSS specific Date: Wed, 28 Oct 2015 15:13:39 +0200 Message-Id: <1446038023-8819-1-git-send-email-jarkko.nikula@linux.intel.com> X-Mailer: git-send-email 2.6.1 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Rename a few defines that are specific to Intel LPSS SPI private registers with LPSS prefix. It makes easier to distinguish them from common defines. Suggested-by: Robert Jarzmik Signed-off-by: Jarkko Nikula --- drivers/spi/spi-pxa2xx.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 672963653d3b..affa05e90411 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -61,9 +61,9 @@ MODULE_ALIAS("platform:pxa2xx-spi"); | QUARK_X1000_SSCR1_TFT \ | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) -#define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) -#define SPI_CS_CONTROL_SW_MODE BIT(0) -#define SPI_CS_CONTROL_CS_HIGH BIT(1) +#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) +#define LPSS_CS_CONTROL_SW_MODE BIT(0) +#define LPSS_CS_CONTROL_CS_HIGH BIT(1) struct lpss_config { /* LPSS offset from drv_data->ioaddr */ @@ -250,8 +250,8 @@ static void lpss_ssp_setup(struct driver_data *drv_data) /* Enable software chip select control */ value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); - value &= ~(SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH); - value |= SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; + value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH); + value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH; __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); /* Enable multiblock DMA transfers */ @@ -261,7 +261,7 @@ static void lpss_ssp_setup(struct driver_data *drv_data) if (config->reg_general >= 0) { value = __lpss_ssp_read_priv(drv_data, config->reg_general); - value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE; + value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE; __lpss_ssp_write_priv(drv_data, config->reg_general, value); } @@ -277,9 +277,9 @@ static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); if (enable) - value &= ~SPI_CS_CONTROL_CS_HIGH; + value &= ~LPSS_CS_CONTROL_CS_HIGH; else - value |= SPI_CS_CONTROL_CS_HIGH; + value |= LPSS_CS_CONTROL_CS_HIGH; __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); }