From patchwork Wed Oct 28 13:13:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jarkko Nikula X-Patchwork-Id: 7510531 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B7CCE9F327 for ; Wed, 28 Oct 2015 13:14:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DECFA20719 for ; Wed, 28 Oct 2015 13:14:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E5BE320711 for ; Wed, 28 Oct 2015 13:14:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965580AbbJ1NON (ORCPT ); Wed, 28 Oct 2015 09:14:13 -0400 Received: from mga14.intel.com ([192.55.52.115]:19351 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751023AbbJ1NOK (ORCPT ); Wed, 28 Oct 2015 09:14:10 -0400 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP; 28 Oct 2015 06:13:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,210,1444719600"; d="scan'208";a="805489166" Received: from mylly.fi.intel.com (HELO mylly.fi.intel.com.) ([10.237.72.53]) by orsmga001.jf.intel.com with ESMTP; 28 Oct 2015 06:13:46 -0700 From: Jarkko Nikula To: linux-spi@vger.kernel.org Cc: Mark Brown , Daniel Mack , Haojian Zhuang , Robert Jarzmik , Jarkko Nikula Subject: [PATCH 2/5] spi: pxa2xx: Add output control for multiple Intel LPSS chip selects Date: Wed, 28 Oct 2015 15:13:40 +0200 Message-Id: <1446038023-8819-2-git-send-email-jarkko.nikula@linux.intel.com> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1446038023-8819-1-git-send-email-jarkko.nikula@linux.intel.com> References: <1446038023-8819-1-git-send-email-jarkko.nikula@linux.intel.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Intel LPSS SPI host controllers in upcoming Intel platforms can have up to 4 chip selects per port. Extend chip select control in lpss_ssp_cs_control() by adding a code that selects the active chip select output prior to changing the state. Detection for number of enabled chip select signals will be added by another patch. Signed-off-by: Jarkko Nikula --- drivers/spi/spi-pxa2xx.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index affa05e90411..019f4dda2cf2 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -64,6 +64,8 @@ MODULE_ALIAS("platform:pxa2xx-spi"); #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) #define LPSS_CS_CONTROL_SW_MODE BIT(0) #define LPSS_CS_CONTROL_CS_HIGH BIT(1) +#define LPSS_CS_CONTROL_CS_SEL_SHIFT 8 +#define LPSS_CS_CONTROL_CS_SEL_MASK (3 << LPSS_CS_CONTROL_CS_SEL_SHIFT) struct lpss_config { /* LPSS offset from drv_data->ioaddr */ @@ -271,15 +273,34 @@ static void lpss_ssp_setup(struct driver_data *drv_data) static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) { const struct lpss_config *config; - u32 value; + u32 value, cs; config = lpss_get_config(drv_data); value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); - if (enable) + if (enable) { + cs = drv_data->cur_msg->spi->chip_select; + cs <<= LPSS_CS_CONTROL_CS_SEL_SHIFT; + if (cs != (value & LPSS_CS_CONTROL_CS_SEL_MASK)) { + /* + * When switching another chip select output active + * the output must be selected first and wait 2 ssp_clk + * cycles before changing state to active. Otherwise + * a short glitch will occur on the previous chip + * select since output select is latched but state + * control is not. + */ + value &= ~LPSS_CS_CONTROL_CS_SEL_MASK; + value |= cs; + __lpss_ssp_write_priv(drv_data, + config->reg_cs_ctrl, value); + ndelay(1000000000 / + (drv_data->master->max_speed_hz / 2)); + } value &= ~LPSS_CS_CONTROL_CS_HIGH; - else + } else { value |= LPSS_CS_CONTROL_CS_HIGH; + } __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); }