From patchwork Sun Nov 1 14:41:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Bondarenko X-Patchwork-Id: 7532191 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D3B2C9F2F7 for ; Sun, 1 Nov 2015 14:42:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DD79B205F7 for ; Sun, 1 Nov 2015 14:42:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A61CA206C0 for ; Sun, 1 Nov 2015 14:42:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752728AbbKAOma (ORCPT ); Sun, 1 Nov 2015 09:42:30 -0500 Received: from mail-lf0-f67.google.com ([209.85.215.67]:36649 "EHLO mail-lf0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752500AbbKAOlr (ORCPT ); Sun, 1 Nov 2015 09:41:47 -0500 Received: by lffz202 with SMTP id z202so4861184lff.3; Sun, 01 Nov 2015 06:41:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fkC0xNB2I0HNwsXviDAD65q6WQgzR7C52vOuDmzPCas=; b=DNCj5ZhJjEm91jrhkquPUqB/eQG+1S6ldJKzl9WQbjHtGpEtnXJ88urZQZrwUhRbIp sSMBjq8g2sXhbxZKWoccV0IiEDpqRLzKwdwLZNYpNee6lJ57hG8jC8oNwulZYLxuE62L gBrvf61RjLNQIew1mNacxxZUvQq+6RGIBVu3wyzQGS9/ONuQPV2SVvbVZlnIc/rydd01 +mONaB9Qe0l7AA/5cpaNAyrKhvLDMnB2P+r4HftND5ubEJ0ywlbd+N0XO3IAxX9FATVj K6ey8a36J1Mgo6E+J8p6BK1ETNZFugD+IsTrBXRf4WOTzp1Zjgq7h680u+N8GkdFfPDm 35dg== X-Received: by 10.25.21.89 with SMTP id l86mr5394735lfi.121.1446388905654; Sun, 01 Nov 2015 06:41:45 -0800 (PST) Received: from localhost.localdomain (c-89-233-200-205.cust.bredband2.com. [89.233.200.205]) by smtp.gmail.com with ESMTPSA id oy8sm3091607lbb.39.2015.11.01.06.41.44 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 01 Nov 2015 06:41:45 -0800 (PST) From: Anton Bondarenko To: broonie@kernel.org, b38343@freescale.com Cc: linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, vladimir_zapolskiy@mentor.com, jiada_wang@mentor.com, s.hauer@pengutronix.de Subject: [PATCH v3 2/7] spi: imx: replace fixed timeout with calculated one Date: Sun, 1 Nov 2015 15:41:36 +0100 Message-Id: <1446388901-6073-3-git-send-email-anton.bondarenko.sama@gmail.com> X-Mailer: git-send-email 2.6.2 In-Reply-To: <1446388901-6073-1-git-send-email-anton.bondarenko.sama@gmail.com> References: <1446388901-6073-1-git-send-email-anton.bondarenko.sama@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Anton Bondarenko Fixed timeout value can fire while transaction is ongoing. This may happen because there are no strict requirements on SPI transaction duration. Dynamic timeout value is generated based on SCLK and transaction size. There is also 4 * SCLK delay between TX bursts related to CS change. Signed-off-by: Anton Bondarenko --- drivers/spi/spi-imx.c | 49 +++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 41 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index bd7b721..9b80c7f 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -57,7 +57,6 @@ /* The maximum bytes that a sdma BD can transfer.*/ #define MAX_SDMA_BD_BYTES (1 << 15) -#define IMX_DMA_TIMEOUT (msecs_to_jiffies(3000)) struct spi_imx_config { unsigned int speed_hz; unsigned int bpw; @@ -93,6 +92,7 @@ struct spi_imx_data { struct clk *clk_per; struct clk *clk_ipg; unsigned long spi_clk; + unsigned int spi_bus_clk; unsigned int count; void (*tx)(struct spi_imx_data *); @@ -314,8 +314,7 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, { u32 ctrl = MX51_ECSPI_CTRL_ENABLE, dma = 0; u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); - - u32 clk = config->speed_hz, delay; + u32 delay; /* * The hardware seems to have a race condition when changing modes. The @@ -327,7 +326,9 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, ctrl |= MX51_ECSPI_CTRL_MODE_MASK; /* set clock speed */ - ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz, &clk); + spi_imx->spi_bus_clk = config->speed_hz; + ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz, + &spi_imx->spi_bus_clk); /* set chip select to use */ ctrl |= MX51_ECSPI_CTRL_CS(config->cs); @@ -367,7 +368,7 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, * the SPI communication as the device on the other end would consider * the change of SCLK polarity as a clock tick already. */ - delay = (2 * 1000000) / clk; + delay = (2 * USEC_PER_SEC) / spi_imx->spi_bus_clk; if (likely(delay < 10)) /* SCLK is faster than 100 kHz */ udelay(delay); else /* SCLK is _very_ slow */ @@ -890,12 +891,40 @@ static void spi_imx_dma_tx_callback(void *cookie) complete(&spi_imx->dma_tx_completion); } +static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size) +{ + unsigned long coef1 = 1; + unsigned long coef2 = MSEC_PER_SEC; + unsigned long timeout = 0; + + /* Swap coeficients to avoid div by 0 */ + if (spi_imx->spi_bus_clk < MSEC_PER_SEC) { + coef1 = MSEC_PER_SEC; + coef2 = 1; + } + + /* Time with actual data transfer */ + timeout += DIV_ROUND_UP(8 * size * coef1, + spi_imx->spi_bus_clk / coef2); + + /* Take CS change delay related to HW */ + timeout += DIV_ROUND_UP((size - 1) * 4 * coef1, + spi_imx->spi_bus_clk / coef2); + + /* Add extra second for scheduler related activities */ + timeout += MSEC_PER_SEC; + + /* Double calculated timeout */ + return msecs_to_jiffies(2 * timeout); +} + static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, struct spi_transfer *transfer) { struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; int ret; unsigned long timeout; + unsigned long transfer_timeout; const int left = transfer->len % spi_imx->wml; struct spi_master *master = spi_imx->bitbang.master; struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; @@ -956,9 +985,11 @@ static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, dma_async_issue_pending(master->dma_tx); spi_imx->devtype_data->trigger(spi_imx); + transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); + /* Wait SDMA to finish the data transfer.*/ timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, - IMX_DMA_TIMEOUT); + transfer_timeout); if (!timeout) { pr_warn("%s %s: I/O Error in DMA TX\n", dev_driver_string(&master->dev), @@ -966,8 +997,10 @@ static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, dmaengine_terminate_all(master->dma_tx); dmaengine_terminate_all(master->dma_rx); } else { + transfer_timeout = spi_imx_calculate_timeout(spi_imx, + spi_imx->wml); timeout = wait_for_completion_timeout( - &spi_imx->dma_rx_completion, IMX_DMA_TIMEOUT); + &spi_imx->dma_rx_completion, transfer_timeout); if (!timeout) { pr_warn("%s %s: I/O Error in DMA RX\n", dev_driver_string(&master->dev), @@ -989,7 +1022,7 @@ static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TCEN); timeout = wait_for_completion_timeout( - &spi_imx->xfer_done, IMX_DMA_TIMEOUT); + &spi_imx->xfer_done, transfer_timeout); if (!timeout) { pr_warn("%s %s: I/O Error in RX tail\n", dev_driver_string(&master->dev),