From patchwork Sun Dec 13 23:04:11 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcus Weseloh X-Patchwork-Id: 7840031 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 237649F1C2 for ; Sun, 13 Dec 2015 23:04:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 319E52046F for ; Sun, 13 Dec 2015 23:04:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4454B20465 for ; Sun, 13 Dec 2015 23:04:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751542AbbLMXEr (ORCPT ); Sun, 13 Dec 2015 18:04:47 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:36408 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751061AbbLMXEp (ORCPT ); Sun, 13 Dec 2015 18:04:45 -0500 Received: by wmdv136 with SMTP id v136so5890929wmd.3; Sun, 13 Dec 2015 15:04:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GzTaEfgmJcvUFrn5FDjQJe7Eag8N60SDXC0XDH5LwuU=; b=fDnpbwdK/OjRRqpEBqx3MRquJp8RJAjtasohHHz8aQkK0IsM/vSNJ2uX6F1gr8ObZz uNmeN+0vBPgWyvXA2MWYHmyXcOrzan9Be+zEwqrqeVR0qMTHzmv6QTSS73ajvKdBPvba 5lDlX5A4cMd33GVwj12Y+vxL7v/PrghsetGjLO5nXgJXKITKk+NEA53m37sLn+vCgwAV KVuKsZRFtHtFcEyD4MGYf59hHLXB38F9VmL3iuyBBfNuWlYfjQDm0+NXk5I0beQabwDu 1XuFe9PBSPvjJx6JKv/KBuAwwBOIGUfyERR8e5MxBLmRy+DDBLdOi7TpnlktVf+DE7PJ SWGg== X-Received: by 10.28.97.197 with SMTP id v188mr21444097wmb.63.1450047884219; Sun, 13 Dec 2015 15:04:44 -0800 (PST) Received: from speedy.fritz.box (p578E9CB4.dip0.t-ipconnect.de. [87.142.156.180]) by smtp.gmail.com with ESMTPSA id da10sm27001747wjb.22.2015.12.13.15.04.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 13 Dec 2015 15:04:42 -0800 (PST) From: Marcus Weseloh To: linux-sunxi@googlegroups.com Cc: Marcus Weseloh , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Mark Brown , Maxime Ripard , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3] spi: dts: sun4i: Add support for hardware-based wait time between words Date: Mon, 14 Dec 2015 00:04:11 +0100 Message-Id: <1450047853-9005-1-git-send-email-mweseloh42@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1449873940-10167-1-git-send-email-mweseloh42@gmail.com> References: <1449873940-10167-1-git-send-email-mweseloh42@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds a new property "spi-word-wait-ns" to the spi-bus binding that allows SPI slave devices to set a hardware based wait time between the transmission of words. Also modifies the sun4i SPI master driver to make use of the new property. This specific SPI controller needs 3 clock cycles to set up the delay, which makes the minimum non-zero wait time on this hardware 4 clock cycles. Signed-off-by: Marcus Weseloh --- Changes from v1: * renamed the property for more clarity * wait time is set in nanoseconds instead of number of clock cycles * transparently handle the 3 setup clock cycles Changes from v2: * fixed typo in comment * moved parameter to spi-bus binding, dropping the vendor prefix * changed commit summary and description to reflect the changes --- Documentation/devicetree/bindings/spi/spi-bus.txt | 2 ++ drivers/spi/spi-sun4i.c | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt index bbaa857..2d6034f 100644 --- a/Documentation/devicetree/bindings/spi/spi-bus.txt +++ b/Documentation/devicetree/bindings/spi/spi-bus.txt @@ -61,6 +61,8 @@ contain the following properties. used for MOSI. Defaults to 1 if not present. - spi-rx-bus-width - (optional) The bus width(number of data wires) that used for MISO. Defaults to 1 if not present. +- spi-word-wait-ns - (optional) Hardware based delay between transmission of + words in nanoseconds Some SPI controllers and devices support Dual and Quad SPI transfer mode. It allows data in the SPI system to be transferred in 2 wires(DUAL) or 4 wires(QUAD). diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c index f60a6d6..73995a1 100644 --- a/drivers/spi/spi-sun4i.c +++ b/drivers/spi/spi-sun4i.c @@ -19,6 +19,7 @@ #include #include #include +#include #include @@ -173,6 +174,9 @@ static int sun4i_spi_transfer_one(struct spi_master *master, unsigned int tx_len = 0; int ret = 0; u32 reg; + u32 wait_ns = 0; + int wait_clk = 0; + int clk_ns = 0; /* We don't support transfer larger than the FIFO */ if (tfr->len > SUN4I_FIFO_DEPTH) @@ -261,6 +265,25 @@ static int sun4i_spi_transfer_one(struct spi_master *master, sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg); + /* Setup wait time between words */ + of_property_read_u32(spi->dev.of_node, "spi-word-wait-ns", + &wait_ns); + if (wait_ns) { + /* The wait time is set in SPI_CLK cycles. The SPI hardware + * needs 3 additional cycles to setup the wait counter, so + * the minimum delay time is 4 cycles. + */ + clk_ns = DIV_ROUND_UP(1000000000, tfr->speed_hz); + wait_clk = DIV_ROUND_UP(wait_ns, clk_ns) - 3; + if (wait_clk < 1) { + wait_clk = 1; + dev_info(&spi->dev, + "using minimum of 4 word wait cycles (%uns)", + 4 * clk_ns); + } + } + sun4i_spi_write(sspi, SUN4I_WAIT_REG, (u16)wait_clk); + /* Setup the transfer now... */ if (sspi->tx_buf) tx_len = tfr->len;