From patchwork Thu Dec 17 11:40:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcus Weseloh X-Patchwork-Id: 7872221 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5F1689F32E for ; Thu, 17 Dec 2015 11:42:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8AB0E20416 for ; Thu, 17 Dec 2015 11:42:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B1158203F7 for ; Thu, 17 Dec 2015 11:42:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753349AbbLQLlq (ORCPT ); Thu, 17 Dec 2015 06:41:46 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:33630 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966226AbbLQLlo (ORCPT ); Thu, 17 Dec 2015 06:41:44 -0500 Received: by mail-wm0-f67.google.com with SMTP id 123so2773956wmn.0; Thu, 17 Dec 2015 03:41:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3I8qnzkR2qZpSWdh0y/XtTMUmzqL5ZVeBJJ9/WwY0bE=; b=NTpGUzjQULcpNB9y3Q6HOKFKg30haFFEsKP9uzYVmg0HzbJe95BA7GU86kb7+d0qGL spSOaBS3E+yJnqwhcWXr4iBvgIZsZKlymGr+XYrFNoZjO3QXOPxBDdRGOyCy2fdbeVGY 140FWYbrEgFSfVCevYzAQuKmWrNjgcVLfnZlWCjnnHFWn9Rz16xQLsPrjbPZgjdghXVI Pd+PLQYV9MPJl5mD06VFqDOdoFlzOw0NgoYuaXCQaGvBPAlD6HeK59SGH/15W3uJ2oDy u2KbaxCFgxpNOIIoGj8l3h4sE6QtC3vYhxBwpyC8aiw+mdUYNx+BL652Bqx5xlp+NjNR 0bPA== X-Received: by 10.28.194.133 with SMTP id s127mr3652586wmf.53.1450352502536; Thu, 17 Dec 2015 03:41:42 -0800 (PST) Received: from speedy.fritz.box (p5793D05C.dip0.t-ipconnect.de. [87.147.208.92]) by smtp.gmail.com with ESMTPSA id w124sm1961314wmg.17.2015.12.17.03.41.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 17 Dec 2015 03:41:41 -0800 (PST) From: Marcus Weseloh To: linux-sunxi@googlegroups.com Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, Ian Campbell , Kumar Gala , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, Marcus Weseloh , Mark Brown , Mark Rutland , Maxime Ripard , Pawel Moll , Rob Herring Subject: [PATCH v5 2/2] spi: sun4i: Add support for wait time between word transmissions Date: Thu, 17 Dec 2015 12:40:27 +0100 Message-Id: <1450352427-25350-3-git-send-email-mweseloh42@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1450352427-25350-1-git-send-email-mweseloh42@gmail.com> References: <1450352427-25350-1-git-send-email-mweseloh42@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Modifies the sun4i SPI master driver to make use of the "spi-word-wait-ns" property. This specific SPI controller needs 3 clock cycles to set up the delay, which makes the minimum non-zero wait time on this hardware 4 clock cycles. Signed-off-by: Marcus Weseloh --- drivers/spi/spi-sun4i.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c index f60a6d6..3b4f5f4 100644 --- a/drivers/spi/spi-sun4i.c +++ b/drivers/spi/spi-sun4i.c @@ -19,6 +19,7 @@ #include #include #include +#include #include @@ -173,6 +174,8 @@ static int sun4i_spi_transfer_one(struct spi_master *master, unsigned int tx_len = 0; int ret = 0; u32 reg; + int wait_clk = 0; + int clk_ns = 0; /* We don't support transfer larger than the FIFO */ if (tfr->len > SUN4I_FIFO_DEPTH) @@ -261,6 +264,25 @@ static int sun4i_spi_transfer_one(struct spi_master *master, sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg); + /* + * Setup wait time between words. + * + * Wait time is set in SPI_CLK cycles. The SPI hardware needs 3 + * additional cycles to setup the wait counter, so the minimum delay + * time is 4 cycles. + */ + if (spi->word_wait_ns) { + clk_ns = DIV_ROUND_UP(1000000000, tfr->speed_hz); + wait_clk = DIV_ROUND_UP(spi->word_wait_ns, clk_ns) - 3; + if (wait_clk < 1) { + wait_clk = 1; + dev_dbg(&spi->dev, + "using minimum of 4 word wait cycles (%uns)", + 4 * clk_ns); + } + } + sun4i_spi_write(sspi, SUN4I_WAIT_REG, (u16)wait_clk); + /* Setup the transfer now... */ if (sspi->tx_buf) tx_len = tfr->len;