From patchwork Sat Dec 26 15:53:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcus Weseloh X-Patchwork-Id: 7922071 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 31FB1BEEE5 for ; Sat, 26 Dec 2015 15:53:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 89CD320375 for ; Sat, 26 Dec 2015 15:53:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A7B2920373 for ; Sat, 26 Dec 2015 15:53:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754653AbbLZPxc (ORCPT ); Sat, 26 Dec 2015 10:53:32 -0500 Received: from mail-wm0-f51.google.com ([74.125.82.51]:35936 "EHLO mail-wm0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754307AbbLZPx2 (ORCPT ); Sat, 26 Dec 2015 10:53:28 -0500 Received: by mail-wm0-f51.google.com with SMTP id p187so222926889wmp.1; Sat, 26 Dec 2015 07:53:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hVwBo5ZV27Ed70glOFjaFMNil/jEY3SQRZzt18zhbxY=; b=KVw4uwBFOM3FiEW37A/+lEiVMpMBsh3dWf9K7YlDIXACgkLD0hEebUSv2ejcFcWwG/ Qual1C8AHYBqft9rgjPUOqymMUOuJ0QttuHxx87emCm1EydIcGXJInUM4IbdtPMUaNNs Rg49+4oCvxfrR94hl7FJ63XTIFiTmqSSHO1ewmk5iqxH4isKGjxQ9o/HyDxv4gJCP7UM 18Yi364iZKDDoPixtmXBor4n2OzkaYYn7q+iQ53js3I1WbGcA4TMLXRXS1AGXYpT8LZQ 5p5iNhseBveUnk+2dmfnBmIC0/0hlCTme8LLyMp1q93NUAsES0/xB2jQmRXPb8fRIsxu 47Nw== X-Received: by 10.194.85.229 with SMTP id k5mr55816694wjz.100.1451145206774; Sat, 26 Dec 2015 07:53:26 -0800 (PST) Received: from speedy.fritz.box (p5793D053.dip0.t-ipconnect.de. [87.147.208.83]) by smtp.gmail.com with ESMTPSA id l7sm49396737wjx.14.2015.12.26.07.53.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 26 Dec 2015 07:53:25 -0800 (PST) From: Marcus Weseloh To: linux-sunxi@googlegroups.com Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, Ian Campbell , Kumar Gala , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, Marcus Weseloh , Mark Brown , Mark Rutland , Maxime Ripard , Pawel Moll , Rob Herring Subject: [PATCH v6 3/3] spi: sun4i: Add support for wait time between word transmissions Date: Sat, 26 Dec 2015 16:53:06 +0100 Message-Id: <1451145186-14235-4-git-send-email-mweseloh42@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1451145186-14235-1-git-send-email-mweseloh42@gmail.com> References: <1451145186-14235-1-git-send-email-mweseloh42@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Modifies the sun4i SPI master driver to make use of the "spi-word-wait-ns" property. This specific SPI controller needs 3 clock cycles to set up the delay, which makes the minimum non-zero wait time on this hardware 4 clock cycles. Signed-off-by: Marcus Weseloh Acked-by: Maxime Ripard --- drivers/spi/spi-sun4i.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c index d67e142..4d6f77c 100644 --- a/drivers/spi/spi-sun4i.c +++ b/drivers/spi/spi-sun4i.c @@ -176,6 +176,9 @@ static int sun4i_spi_transfer_one(struct spi_master *master, unsigned int tx_len = 0; int ret = 0; u32 reg; + int wait_clk = 0; + int clk_ns = 0; + unsigned int speed_hz; /* We don't support transfer larger than the FIFO */ if (tfr->len > SUN4I_FIFO_DEPTH) @@ -260,13 +263,34 @@ static int sun4i_spi_transfer_one(struct spi_master *master, div = DIV_ROUND_UP(mclk_rate, 2 * tfr->speed_hz) - 1; if (div <= SUN4I_CLK_CTL_CDR2_MASK) { reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS; + speed_hz = mclk_rate / (2 * (div + 1)); } else { div = ilog2(roundup_pow_of_two(mclk_rate / tfr->speed_hz)); reg = SUN4I_CLK_CTL_CDR1(div); + speed_hz = mclk_rate / (1 << div); } sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg); + /* + * Setup wait time between words. + * + * Wait time is set in SPI_CLK cycles. The SPI hardware needs 3 + * additional cycles to setup the wait counter, so the minimum delay + * time is 4 cycles. + */ + if (spi->word_wait_ns) { + clk_ns = DIV_ROUND_UP(1000000000, speed_hz); + wait_clk = DIV_ROUND_UP(spi->word_wait_ns, clk_ns) - 3; + if (wait_clk < 1) { + wait_clk = 1; + dev_dbg(&spi->dev, + "using minimum of 4 word wait cycles (%uns)", + 4 * clk_ns); + } + } + sun4i_spi_write(sspi, SUN4I_WAIT_REG, (u16)wait_clk); + /* Setup the transfer now... */ if (sspi->tx_buf) tx_len = tfr->len;