From patchwork Thu Feb 4 10:30:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jarkko Nikula X-Patchwork-Id: 8217781 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 706BB9F3CD for ; Thu, 4 Feb 2016 10:31:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8BDC32034C for ; Thu, 4 Feb 2016 10:31:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9B6C820395 for ; Thu, 4 Feb 2016 10:31:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755888AbcBDKbI (ORCPT ); Thu, 4 Feb 2016 05:31:08 -0500 Received: from mga03.intel.com ([134.134.136.65]:43652 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755959AbcBDKbG (ORCPT ); Thu, 4 Feb 2016 05:31:06 -0500 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP; 04 Feb 2016 02:31:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,395,1449561600"; d="scan'208";a="647054648" Received: from mylly.fi.intel.com (HELO mylly.fi.intel.com.) ([10.237.72.154]) by FMSMGA003.fm.intel.com with ESMTP; 04 Feb 2016 02:31:03 -0800 From: Jarkko Nikula To: linux-spi@vger.kernel.org Cc: Mark Brown , Daniel Mack , Haojian Zhuang , Robert Jarzmik , Andy Shevchenko , Mika Westerberg , Jarkko Nikula Subject: [PATCH 2/2] spi: pxa2xx: Fix too early chipselect deassert Date: Thu, 4 Feb 2016 12:30:57 +0200 Message-Id: <1454581857-12921-2-git-send-email-jarkko.nikula@linux.intel.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1454581857-12921-1-git-send-email-jarkko.nikula@linux.intel.com> References: <1454581857-12921-1-git-send-email-jarkko.nikula@linux.intel.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There is a chance that chipselect is deasserted too early while the last clock cycle is still running. Protocol analyzers will see this as a failed last byte. This is more likely to occur with slow bitrates, for instance at 25 kbps. Reason for this is when using SPI mode 0 that both SPI host controller and SPI slave will drive the data lines at the falling edge of clock signal and sample at the rising edge. Receive FIFO gets the last bit now at the rising edge and code sees transfer to be finished either by the interrupt in PIO mode or by the DMA completion in DMA mode. The SSP Time Out register SSTO should take care of delaying the completion but it does not seems to have effect at least on Intel Skylake and Broxton even when using long enough values. Depending on timing code may get into point where chipselect is deasserted while the last clock cycle is still running at its second half cycle. Fix this by adding a wait loop in giveback() that waits until SSP becomes idle before deasserting the chipselect. Reported-by: Weifeng Voon Signed-off-by: Jarkko Nikula --- For normal development cycle. This is not a fatal issue and I guess real SPI slaves may not hickup because of it. But you never know. --- drivers/spi/spi-pxa2xx.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 9b9a528a9fbd..ce66cf44bba5 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -496,6 +496,7 @@ static void giveback(struct driver_data *drv_data) { struct spi_transfer* last_transfer; struct spi_message *msg; + unsigned long timeout; msg = drv_data->cur_msg; drv_data->cur_msg = NULL; @@ -508,6 +509,12 @@ static void giveback(struct driver_data *drv_data) if (last_transfer->delay_usecs) udelay(last_transfer->delay_usecs); + /* Wait until SSP becomes idle before deasserting the CS */ + timeout = jiffies + msecs_to_jiffies(10); + while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY && + !time_after(jiffies, timeout)) + cpu_relax(); + /* Drop chip select UNLESS cs_change is true or we are returning * a message with an error, or next message is for another chip */