From patchwork Wed May 11 15:29:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 9071901 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E637C9F1C3 for ; Wed, 11 May 2016 15:29:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C228A20145 for ; Wed, 11 May 2016 15:29:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 91ADC200F2 for ; Wed, 11 May 2016 15:29:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932228AbcEKP3v (ORCPT ); Wed, 11 May 2016 11:29:51 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:33158 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751338AbcEKP3h (ORCPT ); Wed, 11 May 2016 11:29:37 -0400 Received: by mail-pf0-f195.google.com with SMTP id y7so3998205pfb.0 for ; Wed, 11 May 2016 08:29:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=0r8UUTMWrBbLEA6/BpiJwBFXqjoOV4wyTFIPrimGwew=; b=B16z5c2Dmlw5w8jF7keiqOYint0xp+Xn2siBGKFIqS8j0wTChgotFEUC6MT4PFwDVg q1ejrhUV84YqjlTxIhf+C86I0mp5OMMQVD3wylE0lfv8ArCQ4VrXS7jq7YHOWKpI3Efc G+tr7IhxFngbeGoUKgCvu6wHCrqESpmo2A+F2XFGXJr9OlSlFw5vv9LpzSLVBOuV91RA Nuy2uExUmkzbrkvMVQTXl5vfo7PsHa5tpsDuLSLh0sg83u0itCLMfKygl1zg33kwF4QO FKSbf9KuB0tKpYVysK950dElommklHnG6jgbOFXxo5KGCy/M3MkUY5peUNkJi7V1SMQO o/zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=0r8UUTMWrBbLEA6/BpiJwBFXqjoOV4wyTFIPrimGwew=; b=lg91HkMF+2shTpxaQC/Wih1t0NzyCv0iURG71Yv6FdvlTPp67iVr/DWiGY9j/BedIZ 2CutsZd9pR4bXj4nkw5HfiR17MguwBu6zmAcdtmIyeXQERU6tRWJ+kAseRW69L1/1DN1 yNrTeQo4RvSVGb64F64I2Mk6S3K3TbLcV/wxgsXyp/u5fgt9lGB7LgRThrjyRUmOIa0d xNJtXsQK9lFigzQVwtuc/nGQv6C1GZ/RC9sDDQgWWxyGVeE0UCzUu5MjCB82opF/uZrH 9K1Exb+uVrF1bh0yQscTowNcxLk1MBVI3ddR+RQVZ3ZuX1T420SV2YJm9HKczIXKZDxo dkPw== X-Gm-Message-State: AOPr4FVEx36cQ0rGgZseEqZqCn1JgQtPgzsDveWREwDpDh80tYAdxQNnbE6Sr5qFm4eIXQ== X-Received: by 10.98.19.131 with SMTP id 3mr5858745pft.17.1462980576888; Wed, 11 May 2016 08:29:36 -0700 (PDT) Received: from mail.broadcom.com ([216.31.219.19]) by smtp.gmail.com with ESMTPSA id 71sm13072283pfy.32.2016.05.11.08.29.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 May 2016 08:29:35 -0700 (PDT) From: Kamal Dasu To: linux-spi@vger.kernel.org, f.fainelli@gmail.com Cc: bcm-kernel-feedback-list@broadcom.com, vikram.prakash@broadcom.com, andy.fung@broadcom.com, jon.mason@broadcom.com, Kamal Dasu , Yendapally Reddy Dhananjaya Reddy Subject: [PATCH 1/4] dt: bindings: spi-bcm-qspi: NSP, NS2, BRCMSTB SoC bindings Date: Wed, 11 May 2016 11:29:24 -0400 Message-Id: <1462980567-310-1-git-send-email-kdasu.kdev@gmail.com> X-Mailer: git-send-email 1.9.1 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Added device tree bindings documentation for SoCs supported by the new spi-bcm-qspi driver. Signed-off-by: Kamal Dasu Signed-off-by: Yendapally Reddy Dhananjaya Reddy --- .../devicetree/bindings/spi/spi-bcm-qspi.txt | 228 +++++++++++++++++++++ 1 file changed, 228 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-bcm-qspi.txt diff --git a/Documentation/devicetree/bindings/spi/spi-bcm-qspi.txt b/Documentation/devicetree/bindings/spi/spi-bcm-qspi.txt new file mode 100644 index 0000000..a79a384 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-bcm-qspi.txt @@ -0,0 +1,228 @@ +Broadcom SPI controller + +The Broadcom SPI controller is a SPI master found on various SOCs, including +BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. + +Required properties: + +- #address-cells: + Must be <1>, as required by generic SPI binding. + +- #size-cells: + Must be <0>, also as required by generic SPI binding. + +- compatible: + Must be one of : + "brcm,spi-bcm-qspi" + "brcm,spi-brmstb" spi-nor and/or "brcm,spi-brmstb-mspi" unmanaged SPI Master + +- reg: + Define the bases and ranges of the associated I/O address spaces. + The required range is MSPI controller registers and interrupt registers, the others + are optional Boot SPI (BSPI) portion for fast flash reads. + +- reg-names: + First name does not matter, but must be reserved for the MSPI controller + register range as mentioned in 'reg' above, and will typically contain + - "bspi_regs": BSPI register range + - "mspi_regs": MSPI register range + - "intr_regs", "intr_status_reg" : Interrupt and status register for NSP, NS2 SoC + - "hif_spi_intr2" : Interrupt and status register for BRCMSTB SoC + +- interrupts + The interrupts used by the MSPI and/or BSPI controller. + +- interrupt-names: + Names of interrupts associated with this MSPI and/or BSPI controller. + - "mspi_halted" : + - "mspi_done": Indicates that the requested SPI operation is complete. + - "spi_lr_fullness_reached" : Linear read BSPI pipe full + - "spi_lr_session_aborted" : Linear read BSPI pipe aborted + - "spi_lr_impatient" : Linear read BSPI requested when pipe empty + - "spi_lr_session_done" : Linear read BSPI session done + +Optional properties: + +- clocks: + A phandle to the reference clock for this block. If not present, will + assume a 27 MHz fixed clock (default for UPG). + + +Optional properties: + +- clocks: + A phandle to the reference clock for this block. + +- bspi-sel: + Chip selects that requires bspi support. + + +Examples: + +BRCMSTB SoC Example: + + SPI Master for SPI-NOR: + + spi@f03e3400 { + #address-cells = <0x1>; + #size-cells = <0x0>; + compatible = "brcm,qspi-brcmstb"; + reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>; + reg-names = "cs_reg", "hif_mspi", "bspi"; + interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>; + interrupt-parent = <0x1c>; + interrupt-names = "mspi_halted", + "mspi_done", + "spi_lr_overread", + "spi_lr_session_done", + "spi_lr_impatient", + "spi_lr_session_aborted", + "spi_lr_fullness_reached"; + + clocks = <0x1b>; + clock-names = "sw_spi"; + + m25p80@0 { + #size-cells = <0x2>; + #address-cells = <0x2>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <0x2625a00>; + spi-cpol; + spi-cpha; + use-bspi; + m25p,fast-read; + + flash0.bolt@0 { + reg = <0x0 0x0 0x0 0x100000>; + }; + + flash0.macadr@100000 { + reg = <0x0 0x100000 0x0 0x10000>; + }; + + flash0.nvram@110000 { + reg = <0x0 0x110000 0x0 0x10000>; + }; + + flash0.kernel@120000 { + reg = <0x0 0x120000 0x0 0x400000>; + }; + + flash0.devtree@520000 { + reg = <0x0 0x520000 0x0 0x10000>; + }; + + flash0.splash@530000 { + reg = <0x0 0x530000 0x0 0x80000>; + }; + + flash0@0 { + reg = <0x0 0x0 0x0 0x4000000>; + }; + }; + }; + + + MSPI master: + + spi@f0416000 { + #address-cells = <1>; + #size-cells = <0>; + clocks = <&upg_fixed>; + compatible = "brcm,spi-brcmstb-mspi"; + reg = <0xf0416000 0x180>; + reg-names = "mspi"; + interrupts = <0x14>; + interrupt-parent = <&irq0_aon_intc>; + interrupt-names = "mspi_done"; + }; + + + +iProc SoC Example: + + qspi: spi@18027200 { + compatible = "brcm,spi-bcm-qspi"; + reg = <0x18027200 0x184>, + <0x18027000 0x124>, + <0x1811c408 0x004>, + <0x180273a0 0x01c>; + reg-names = "mspi_regs", "bspi_regs", "intr_regs", "intr_status_reg"; + interrupts = , + , + , + , + , + , + ; + interrupt-names = + "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "mspi_done", + "mspi_halted"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + clock-frequency = <12500000>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + + NS2 SoC Example: + + qspi: spi@66470200 { + compatible = "brcm,spi-bcm-qspi"; + reg = <0x66470200 0x184>, + <0x66470000 0x124>, + <0x67017408 0x004>, + <0x664703a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; + interrupts = ; + interrupt-names = "spi_l1_intr"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + clock-frequency = <12500000>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + + m25p80 node for NSP, NS2 and iProc + + &qspi { + bspi-sel = <0>; + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@1 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@2 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@3 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + };