From patchwork Fri Jun 10 20:06:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 9170409 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D5B4D607D9 for ; Fri, 10 Jun 2016 20:06:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C6E9928047 for ; Fri, 10 Jun 2016 20:06:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B9FC828325; Fri, 10 Jun 2016 20:06:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9C87128047 for ; Fri, 10 Jun 2016 20:06:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751719AbcFJUGh (ORCPT ); Fri, 10 Jun 2016 16:06:37 -0400 Received: from mail-pa0-f66.google.com ([209.85.220.66]:36146 "EHLO mail-pa0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751382AbcFJUGg (ORCPT ); Fri, 10 Jun 2016 16:06:36 -0400 Received: by mail-pa0-f66.google.com with SMTP id fg1so5667944pad.3 for ; Fri, 10 Jun 2016 13:06:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=9BN/6sOXs1SskrArdQ1U3aNIEcYlQ3d+Gy/Usu9OeaM=; b=k5firFwPf40bA8/zvv1fwR8KHndH6pJS+fLuw+ii/DycJG9sI9FkaK6Esem45Dz1lN jMJJpAgLkFeOWt/FJK8I78d9+9hoBJeJwCoVUuxkUxsLeqf/I/1q9N/SeI96TRTCurLH +08OkiHk6gWWNZ5T/6PFeK1JZ5ypVUJvUbhmHC/s21FAyqarhL0AiFE/+7NUwAMrtE+N pLDUO3UsuGkTExic3k2ib5VaqTzP1U+StG0OZprn1pHO2YGAlMJpEiN+TNTkcVXIV3EQ dDanVl/8jbiG4zqQwgKaJ+dEhZGgJ1FTPnUCwzy/9MYShZB2ojQ7ubvON2IJOu+giOsg Pbpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=9BN/6sOXs1SskrArdQ1U3aNIEcYlQ3d+Gy/Usu9OeaM=; b=T7vFL1pFazVvLjmfJqkzo1RbsjsEykAzetT/aX0+v+XY2R03SZmxGtXtTt/YlfsOx9 0H6kmUUWkb4PwXbd4oUhw3YvAX8Ts2EApRHwS82H8Y0qHKbiG4HflJP5OBZnimAeVx8+ SeOk1xOAj6Ok+JG/7+sAcadIK/7NdJF5eyRrjEVaabDFWfhmukyTF1HcLYVAetxjm+/w ftC1bO3XRruNaa94vejsB/PYm8R3qg5Tlm58uGuSe1zr9zW1j4yHDwdK9sB+6cpRNV+B Stwdi4hInKCseDMbpZMa3LtWCIy+G653NZxCTpkq6qAVfuN64jLzm0p4qKZKaF+5dTAX 7xpg== X-Gm-Message-State: ALyK8tJ8mffsqkCsjh/c3YfkUodh/QODYInGhvgBAZ4O1UMOMBFhQFeBuTApGplsqPeV8Q== X-Received: by 10.66.55.69 with SMTP id q5mr4146105pap.145.1465589195037; Fri, 10 Jun 2016 13:06:35 -0700 (PDT) Received: from mail.broadcom.com ([216.31.219.19]) by smtp.gmail.com with ESMTPSA id s90sm19563819pfj.86.2016.06.10.13.06.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 10 Jun 2016 13:06:33 -0700 (PDT) From: Kamal Dasu To: linux-spi@vger.kernel.org, f.fainelli@gmail.com, broonie@kernel.org Cc: bcm-kernel-feedback-list@broadcom.com, vikram.prakash@broadcom.com, andy.fung@broadcom.com, jon.mason@broadcom.com, Kamal Dasu , Yendapally Reddy Dhananjaya Reddy Subject: [V3, 1/4] dt: bindings: spi-bcm-qspi: NSP, NS2, BRCMSTB SoC bindings Date: Fri, 10 Jun 2016 16:06:08 -0400 Message-Id: <1465589171-25575-1-git-send-email-kdasu.kdev@gmail.com> X-Mailer: git-send-email 1.9.1 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Added device tree bindings documentation for SoCs supported by the new spi-bcm-qspi driver. Signed-off-by: Kamal Dasu Signed-off-by: Yendapally Reddy Dhananjaya Reddy --- V3 chnage fixes checkpatch errors and warnings V2 change renames file to brcm,spi-bcm-qspi.txt --- .../devicetree/bindings/spi/brcm,spi-bcm-qspi.txt | 227 +++++++++++++++++++++ 1 file changed, 227 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt diff --git a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt new file mode 100644 index 0000000..4c3f7e3 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt @@ -0,0 +1,227 @@ +Broadcom SPI controller + +The Broadcom SPI controller is a SPI master found on various SOCs, including +BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. + +Required properties: + +- #address-cells: + Must be <1>, as required by generic SPI binding. + +- #size-cells: + Must be <0>, also as required by generic SPI binding. + +- compatible: + Must be one of : + "brcm,spi-bcm-qspi" + "brcm,spi-brmstb" spi-nor and/or "brcm,spi-brmstb-mspi" unmanaged SPI Master + +- reg: + Define the bases and ranges of the associated I/O address spaces. + The required range is MSPI controller registers and interrupt registers, the others + are optional Boot SPI (BSPI) portion for fast flash reads. + +- reg-names: + First name does not matter, but must be reserved for the MSPI controller + register range as mentioned in 'reg' above, and will typically contain + - "bspi_regs": BSPI register range + - "mspi_regs": MSPI register range + - "intr_regs", "intr_status_reg" : Interrupt and status register for NSP, NS2 SoC + - "hif_spi_intr2" : Interrupt and status register for BRCMSTB SoC + +- interrupts + The interrupts used by the MSPI and/or BSPI controller. + +- interrupt-names: + Names of interrupts associated with this MSPI and/or BSPI controller. + - "mspi_halted" : + - "mspi_done": Indicates that the requested SPI operation is complete. + - "spi_lr_fullness_reached" : Linear read BSPI pipe full + - "spi_lr_session_aborted" : Linear read BSPI pipe aborted + - "spi_lr_impatient" : Linear read BSPI requested when pipe empty + - "spi_lr_session_done" : Linear read BSPI session done + +Optional properties: + +- clocks: + A phandle to the reference clock for this block. If not present, will + assume a 27 MHz fixed clock (default for UPG). + + +Optional properties: + +- clocks: + A phandle to the reference clock for this block. + +- bspi-sel: + Chip selects that requires bspi support. + +Examples: + +BRCMSTB SoC Example: + + SPI Master for SPI-NOR: + + spi@f03e3400 { + #address-cells = <0x1>; + #size-cells = <0x0>; + compatible = "brcm,qspi-brcmstb"; + reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>; + reg-names = "cs_reg", "hif_mspi", "bspi"; + interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>; + interrupt-parent = <0x1c>; + interrupt-names = "mspi_halted", + "mspi_done", + "spi_lr_overread", + "spi_lr_session_done", + "spi_lr_impatient", + "spi_lr_session_aborted", + "spi_lr_fullness_reached"; + + clocks = <0x1b>; + clock-names = "sw_spi"; + + m25p80@0 { + #size-cells = <0x2>; + #address-cells = <0x2>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <0x2625a00>; + spi-cpol; + spi-cpha; + use-bspi; + m25p,fast-read; + + flash0.bolt@0 { + reg = <0x0 0x0 0x0 0x100000>; + }; + + flash0.macadr@100000 { + reg = <0x0 0x100000 0x0 0x10000>; + }; + + flash0.nvram@110000 { + reg = <0x0 0x110000 0x0 0x10000>; + }; + + flash0.kernel@120000 { + reg = <0x0 0x120000 0x0 0x400000>; + }; + + flash0.devtree@520000 { + reg = <0x0 0x520000 0x0 0x10000>; + }; + + flash0.splash@530000 { + reg = <0x0 0x530000 0x0 0x80000>; + }; + + flash0@0 { + reg = <0x0 0x0 0x0 0x4000000>; + }; + }; + }; + + + MSPI master: + + spi@f0416000 { + #address-cells = <1>; + #size-cells = <0>; + clocks = <&upg_fixed>; + compatible = "brcm,spi-brcmstb-mspi"; + reg = <0xf0416000 0x180>; + reg-names = "mspi"; + interrupts = <0x14>; + interrupt-parent = <&irq0_aon_intc>; + interrupt-names = "mspi_done"; + }; + + + +iProc SoC Example: + + qspi: spi@18027200 { + compatible = "brcm,spi-bcm-qspi"; + reg = <0x18027200 0x184>, + <0x18027000 0x124>, + <0x1811c408 0x004>, + <0x180273a0 0x01c>; + reg-names = "mspi_regs", "bspi_regs", "intr_regs", "intr_status_reg"; + interrupts = , + , + , + , + , + , + ; + interrupt-names = + "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "mspi_done", + "mspi_halted"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + clock-frequency = <12500000>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + + NS2 SoC Example: + + qspi: spi@66470200 { + compatible = "brcm,spi-bcm-qspi"; + reg = <0x66470200 0x184>, + <0x66470000 0x124>, + <0x67017408 0x004>, + <0x664703a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; + interrupts = ; + interrupt-names = "spi_l1_intr"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + clock-frequency = <12500000>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + + m25p80 node for NSP, NS2 and iProc + + &qspi { + bspi-sel = <0>; + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@1 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@2 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@3 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + };