From patchwork Wed Jul 13 19:34:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Girish Mahadevan X-Patchwork-Id: 9228413 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 349BF6088F for ; Wed, 13 Jul 2016 19:35:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2781227FBB for ; Wed, 13 Jul 2016 19:35:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1C0EF28047; Wed, 13 Jul 2016 19:35:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 994082807B for ; Wed, 13 Jul 2016 19:35:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750983AbcGMTfD (ORCPT ); Wed, 13 Jul 2016 15:35:03 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:48545 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751091AbcGMTe4 (ORCPT ); Wed, 13 Jul 2016 15:34:56 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 2AE34611CC; Wed, 13 Jul 2016 19:34:51 +0000 (UTC) Received: from girishm-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: girishm@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1EDB260388; Wed, 13 Jul 2016 19:34:50 +0000 (UTC) From: Girish Mahadevan To: broonie@kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: sboyd@codeaurora.org, sdharia@codeaurora.org, girishm@codeaurora.org, linux-arm-msm@vger.kernel.org Subject: [PATCH RFCv1 1/1] spi: Expand tx_nbits/rx_nbits to add 8-bit transfer Date: Wed, 13 Jul 2016 13:34:37 -0600 Message-Id: <1468438477-18883-2-git-send-email-girishm@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1468438477-18883-1-git-send-email-girishm@codeaurora.org> References: <1468438477-18883-1-git-send-email-girishm@codeaurora.org> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Expand the tx_nbits/rx_nbits member of the spi_transfer struct to a 4 bit value to allow specifying 8 bit transfers (SPI_NBITS_OCTO). Change-Id: I0b7ab41b2caa8495da431944ccbc0b90942d5dd9 Signed-off-by: Girish Mahadevan --- include/linux/spi/spi.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 857a9a1..45b958a 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -717,10 +717,11 @@ extern void spi_res_release(struct spi_master *master, * by the results of previous messages and where the whole transaction * ends when the chipselect goes intactive. * - * When SPI can transfer in 1x,2x or 4x. It can get this transfer information + * When SPI can transfer in 1x,2x,4x or 8x. It can get this transfer information * from device through @tx_nbits and @rx_nbits. In Bi-direction, these * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x) - * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer. + * SPI_NBITS_DUAL(2x) SPI_NBITS_QUAD(4x) and SPI_NBITS_OCTO(8x) to support + * these four transfers. * * The code that submits an spi_message (and its spi_transfers) * to the lower layers is responsible for managing its memory. @@ -744,11 +745,12 @@ struct spi_transfer { struct sg_table rx_sg; unsigned cs_change:1; - unsigned tx_nbits:3; - unsigned rx_nbits:3; + unsigned tx_nbits:4; + unsigned rx_nbits:4; #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */ #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */ #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */ +#define SPI_NBITS_OCTO 0x08 /* 4bits transfer */ u8 bits_per_word; u16 delay_usecs; u32 speed_hz;