From patchwork Fri Jul 29 22:12:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 9252927 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 37C256075F for ; Fri, 29 Jul 2016 22:12:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 27B3828423 for ; Fri, 29 Jul 2016 22:12:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1C7E228435; Fri, 29 Jul 2016 22:12:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9769628423 for ; Fri, 29 Jul 2016 22:12:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754195AbcG2WMn (ORCPT ); Fri, 29 Jul 2016 18:12:43 -0400 Received: from mail-pa0-f66.google.com ([209.85.220.66]:36465 "EHLO mail-pa0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753389AbcG2WMm (ORCPT ); Fri, 29 Jul 2016 18:12:42 -0400 Received: by mail-pa0-f66.google.com with SMTP id ez1so5784930pab.3 for ; Fri, 29 Jul 2016 15:12:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MhJXziyxWqUAcKzYM0H7+oa0+jZp78M73u6vaFFGUsY=; b=yBEl1i3gLOicooL76vaF4xxxoqlbuu1QA9yCU5HgjS5/+sxUJ66oke9G2daq+sBHwt Z3rIyB52jMnhdUJyijrghmPwENzsjFiysPLfvOi2HIPxBjM26JQ/aIpvNlL34sKCDwLG kLifXo4INFX2R2/UAzT2fCV/L5sAb3Bg3+n1i3Vkn+Cabde4sGpmRb4j+gYjFDKkws9K Wrl7ebYUFNvDJJADTQl72mcVbcFAsByN0kAjVFMaXCwZg7/CiAH0GQJp4LlRKTyQNvYu TmBr2Ijh5hS7baPDaKnqQzA88WvbG0dPud8s0llIjQaVVyOWMFHAprSX7qBRWi9ETzCl yJsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MhJXziyxWqUAcKzYM0H7+oa0+jZp78M73u6vaFFGUsY=; b=T1/J+HaMSVnSf1iabmBnxiCQm+thhGQhWhZ0P6HyATLoEBECRuyfJ7HJYtObw60BtA fX4/kv8UadM1PpIHHJAuxX6cXsaX93CBIq83IPioLDvgfZx9WQ4y++usxCcyumWS7mpK yQOsxcKp/wlDvJidHSS+vGujpsxLIy/462acoi2I8OJPuODidrOYZMr39h+kOcVrHvFd rtQx7RaXEjk9RO3rjP/CJq471iPjBX6ql1uBOk6t9SZomze94Jc8sab91Uovz5/1/Qnf 5+I0Mln1vlaCVPXpD+2WCKf6jAF1ahFBgpYjjEAAFyDqe0V57zFu4DSDhHBQK1O6JtEz i1sw== X-Gm-Message-State: AEkoous86qer7/8qGjdRg6ZsRPad9MM++UDBDfqa0/4rmq2Csy+IHS2132RX2dkQ7jstxg== X-Received: by 10.66.229.9 with SMTP id sm9mr72356006pac.138.1469830361447; Fri, 29 Jul 2016 15:12:41 -0700 (PDT) Received: from mail.broadcom.com ([216.31.219.19]) by smtp.gmail.com with ESMTPSA id d72sm27391258pfj.15.2016.07.29.15.12.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 29 Jul 2016 15:12:40 -0700 (PDT) From: Kamal Dasu To: broonie@kernel.org, linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, vigneshr@ti.com, f.fainelli@gmail.com Cc: bcm-kernel-feedback-list@broadcom.com, vikram.prakash@broadcom.com, andy.fung@broadcom.com, jon.mason@broadcom.com, jchandra@broadcom.com, Kamal Dasu Subject: [PATCH v5 1/8] Documentation: dt: spi: Add BRCMSTB SoC bindings Date: Fri, 29 Jul 2016 18:12:14 -0400 Message-Id: <1469830341-13244-2-git-send-email-kdasu.kdev@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1469830341-13244-1-git-send-email-kdasu.kdev@gmail.com> References: <1469830341-13244-1-git-send-email-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Added device tree bindings documentation for SoCs supported by the new spi-bcm-qspi, spi-brcmstb-qspi driver. Signed-off-by: Kamal Dasu --- .../devicetree/bindings/spi/brcm,spi-bcm-qspi.txt | 145 +++++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt diff --git a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt new file mode 100644 index 0000000..bbae763 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt @@ -0,0 +1,145 @@ +Broadcom SPI controller + +The Broadcom SPI controller is a SPI master found on various SOCs, including +BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits +of : + MSPI : SPI master controller can read and write to a SPI slave device + BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration + for flash reads and be configured to do single, double, quad lane + io with 3-byte and 4-byte addressing support. + + Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP. + MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance + of a MSPI master without the BSPI to use with non flash slave devices that + use SPI protocol. + +Required properties: + +- #address-cells: + Must be <1>, as required by generic SPI binding. + +- #size-cells: + Must be <0>, also as required by generic SPI binding. + +- compatible: + Must be one of : + "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs + "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI + BRCMSTB SoCs + +- reg: + Define the bases and ranges of the associated I/O address spaces. + The required range is MSPI controller registers. + +- reg-names: + First name does not matter, but must be reserved for the MSPI controller + register range as mentioned in 'reg' above, and will typically contain + - "bspi_regs": BSPI register range, not required with compatible + "spi-brcmstb-mspi" + - "mspi_regs": MSPI register range is required for compatible strings + +- interrupts + The interrupts used by the MSPI and/or BSPI controller. + +- interrupt-names: + Names of interrupts associated with MSPI + - "mspi_halted" : + - "mspi_done": Indicates that the requested SPI operation is complete. + - "spi_lr_fullness_reached" : Linear read BSPI pipe full + - "spi_lr_session_aborted" : Linear read BSPI pipe aborted + - "spi_lr_impatient" : Linear read BSPI requested when pipe empty + - "spi_lr_session_done" : Linear read BSPI session done + +- clocks: + A phandle to the reference clock for this block. + +Optional properties: + + +- native-endian + Defined when using BE SoC and device uses BE register read/write + +Recommended optional m25p80 properties: +- spi-rx-bus-width: Definition as per + Documentation/devicetree/bindings/spi/spi-bus.txt + +Examples: + +BRCMSTB SoC Example: + + SPI Master (MSPI+BSPI) for SPI-NOR access: + + spi@f03e3400 { + #address-cells = <0x1>; + #size-cells = <0x0>; + compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-qspi"; + reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>; + reg-names = "cs_reg", "mspi", "bspi"; + interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>; + interrupt-parent = <0x1c>; + interrupt-names = "mspi_halted", + "mspi_done", + "spi_lr_overread", + "spi_lr_session_done", + "spi_lr_impatient", + "spi_lr_session_aborted", + "spi_lr_fullness_reached"; + + clocks = <&hif_spi>; + clock-names = "sw_spi"; + + m25p80@0 { + #size-cells = <0x2>; + #address-cells = <0x2>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <0x2625a00>; + spi-cpol; + spi-cpha; + m25p,fast-read; + + flash0.bolt@0 { + reg = <0x0 0x0 0x0 0x100000>; + }; + + flash0.macadr@100000 { + reg = <0x0 0x100000 0x0 0x10000>; + }; + + flash0.nvram@110000 { + reg = <0x0 0x110000 0x0 0x10000>; + }; + + flash0.kernel@120000 { + reg = <0x0 0x120000 0x0 0x400000>; + }; + + flash0.devtree@520000 { + reg = <0x0 0x520000 0x0 0x10000>; + }; + + flash0.splash@530000 { + reg = <0x0 0x530000 0x0 0x80000>; + }; + + flash0@0 { + reg = <0x0 0x0 0x0 0x4000000>; + }; + }; + }; + + + MSPI master for any SPI device : + + spi@f0416000 { + #address-cells = <1>; + #size-cells = <0>; + clocks = <&upg_fixed>; + compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-mspi"; + reg = <0xf0416000 0x180>; + reg-names = "mspi"; + interrupts = <0x14>; + interrupt-parent = <&irq0_aon_intc>; + interrupt-names = "mspi_done"; + }; +