From patchwork Fri Jul 29 22:13:10 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 9252937 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A4ECE6075F for ; Fri, 29 Jul 2016 22:13:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 953BD28423 for ; Fri, 29 Jul 2016 22:13:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8A4AF28437; Fri, 29 Jul 2016 22:13:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1FDCB28423 for ; Fri, 29 Jul 2016 22:13:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754195AbcG2WNx (ORCPT ); Fri, 29 Jul 2016 18:13:53 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:35687 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752937AbcG2WNx (ORCPT ); Fri, 29 Jul 2016 18:13:53 -0400 Received: by mail-pf0-f193.google.com with SMTP id h186so6041100pfg.2 for ; Fri, 29 Jul 2016 15:13:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8GdquZW9XOorJhDbAofPKM8qUkhbjZSTOmU9MczZYrs=; b=TeRxDh35V54StrauILya1RppgXMIBF7yvmgPA8IyCZhDIsqxrV02Un+UtZFEbE2iOh TfUi9hdvLqJBN2erCHd2wSO9rRssDoe2R8kl+JcFjRaq5bGRfaBHqga1Sk0LKbCwI9Lw xnmm8ZEvUwrDc1WaN27v4V4s0mXJRsfTAUt3qK88da5TAYjYnL7mz15dVGHpYK9p2k+b b1fHAgMAMhN7ITHrKiJAROTAVIUYNFXKPn+DeXF9Meu5065FqYui+neYlnzFOnlPtD64 X12/D0XNEFa2fHPcN2o+ZuqpU1XowCtUDZXNNIn8i2inCP2OGkwXdseEcMPV4Zjxe3Qj JoiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8GdquZW9XOorJhDbAofPKM8qUkhbjZSTOmU9MczZYrs=; b=J0WNZMqdt+WpyNnRPfVilbLB+zVKZf1ww1M9A6SBqBV1rYWV1SC+gZ/08YE7IUPB+k a9JxjtErAeA1Yyp/HsL2gedv8MtQVM1ppi44mwRaLCZFyT7Ni7mXr5kzDkL2T+PxlUMf p0T6CW8jcGdWLfwpyOx1zUuUHt6HbUDYS/xm9ZZxZgsi1qgCkguSLiZLCqFvS9Uo6w0l pMAfd5DfsT1ILbQWveT+zm0MakiBkupxLog6vfn26MVabChtowz3mB3wKoY9FKNPjV+W BnFz0/ML7+VKdNx9SAaP7t0JUm3vCE+JPOtTfG3Sr7OEpPj2aZxUlJvib66EHyCWboRD cTDw== X-Gm-Message-State: AEkoouu+YaJtP8JqpRo/iWIDFrrsSgsZj2aRqHf0Yj1xVEGEE6ucEzOCQFV4GvzJlzTG8g== X-Received: by 10.98.66.209 with SMTP id h78mr73078703pfd.11.1469830432495; Fri, 29 Jul 2016 15:13:52 -0700 (PDT) Received: from mail.broadcom.com ([216.31.219.19]) by smtp.gmail.com with ESMTPSA id zk7sm27207051pac.41.2016.07.29.15.13.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 29 Jul 2016 15:13:51 -0700 (PDT) From: Kamal Dasu To: broonie@kernel.org, linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, vigneshr@ti.com, f.fainelli@gmail.com Cc: bcm-kernel-feedback-list@broadcom.com, vikram.prakash@broadcom.com, andy.fung@broadcom.com, jon.mason@broadcom.com, jchandra@broadcom.com, Kamal Dasu Subject: [PATCH v5 5/8] Documentation: dt: spi: Add Broadcom NSP, NS2 SoC bindings Date: Fri, 29 Jul 2016 18:13:10 -0400 Message-Id: <1469830393-13295-6-git-send-email-kdasu.kdev@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1469830393-13295-1-git-send-email-kdasu.kdev@gmail.com> References: <1469830393-13295-1-git-send-email-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Modify device tree bindings documentation to include NS*, Cygnus and iProc SoCs supported by the new spi-bcm-qspi, spi-nsp-qspi driver. Signed-off-by: Kamal Dasu --- .../devicetree/bindings/spi/brcm,spi-bcm-qspi.txt | 96 +++++++++++++++++++++- 1 file changed, 93 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt index bbae763..bc01b73 100644 --- a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt +++ b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt @@ -5,8 +5,8 @@ BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits of : MSPI : SPI master controller can read and write to a SPI slave device BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration - for flash reads and be configured to do single, double, quad lane - io with 3-byte and 4-byte addressing support. + for flash reads and be configured to do single, double, quad lane + io with 3-byte and 4-byte addressing support. Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP. MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance @@ -26,6 +26,8 @@ Required properties: "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI BRCMSTB SoCs + "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi" : Uses MSPI+BSPI on Cygnus, NSP, + NS2 SoCs - reg: Define the bases and ranges of the associated I/O address spaces. @@ -35,8 +37,10 @@ Required properties: First name does not matter, but must be reserved for the MSPI controller register range as mentioned in 'reg' above, and will typically contain - "bspi_regs": BSPI register range, not required with compatible - "spi-brcmstb-mspi" + "spi-brcmstb-mspi" - "mspi_regs": MSPI register range is required for compatible strings + - "intr_regs", "intr_status_reg" : Interrupt and status register for + NSP, NS2, Cygnus SoC - interrupts The interrupts used by the MSPI and/or BSPI controller. @@ -143,3 +147,89 @@ BRCMSTB SoC Example: interrupt-names = "mspi_done"; }; +iProc SoC Example: + + qspi: spi@18027200 { + compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; + reg = <0x18027200 0x184>, + <0x18027000 0x124>, + <0x1811c408 0x004>, + <0x180273a0 0x01c>; + reg-names = "mspi_regs", "bspi_regs", "intr_regs", "intr_status_reg"; + interrupts = , + , + , + , + , + , + ; + interrupt-names = + "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "mspi_done", + "mspi_halted"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + clock-frequency = <12500000>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + + NS2 SoC Example: + + qspi: spi@66470200 { + compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; + reg = <0x66470200 0x184>, + <0x66470000 0x124>, + <0x67017408 0x004>, + <0x664703a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", + "intr_status_reg"; + interrupts = ; + interrupt-names = "spi_l1_intr"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + clock-frequency = <12500000>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + + m25p80 node for NSP, NS2 + + &qspi { + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@1 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@2 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@3 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + };