From patchwork Fri Feb 10 21:49:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 9567555 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1F44B601EA for ; Fri, 10 Feb 2017 22:10:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 08758285E4 for ; Fri, 10 Feb 2017 22:10:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F1763285E6; Fri, 10 Feb 2017 22:10:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7149C285E4 for ; Fri, 10 Feb 2017 22:10:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751214AbdBJWKT (ORCPT ); Fri, 10 Feb 2017 17:10:19 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:32812 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751081AbdBJWKS (ORCPT ); Fri, 10 Feb 2017 17:10:18 -0500 Received: by mail-wm0-f66.google.com with SMTP id v77so9204591wmv.0 for ; Fri, 10 Feb 2017 14:10:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ba8XWTb2YMOkQcDiqOQ3ZR5OMz+qvByxjAVfFe/PYXk=; b=SKAwDVqyYgYgbL7nApYA05639uhuVTL01XgpR9QYFJLQg6URzig6bITdVsptWbDAtz NeZ4JRipcWcD8cDHcIf2pM7q7mTk4v76LAW8kCh2Vy3ZWL6hFmdAHDk6gXyU9F/cR4Fx dUp2WevY0ML/ipDagtK1smBb5rbMRwABh3FzJ4uXDYhg4AjWkolRNfWMHKvWrhyt2HaQ LEZ2U+slISuvFeCqV519BnEi8AKaNG16lb6h0b/drrS+CvTLRsdqPTL1d+yur72IFkKD fmtg4wBMdJeivUutF4Ywk6FN0mNi91F+h1RyEOPsM1el/jEymCDBPsjooF+ItE3sHrO0 55Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ba8XWTb2YMOkQcDiqOQ3ZR5OMz+qvByxjAVfFe/PYXk=; b=GWALeYUYmywrbz1MbvomJ+mNCJBtmGCJ3bUgcCkhCgelRcaGE52VKtSW+5dE0C/+mV MFy7HYfJg47jqbN5UOuHI54XmmeG86C2ZSFEnOS4qNlH1gMTmxfSbO8XPpwtpLtxlKBE 9rIhXxn58AcjbabwYKkPkakVNq7hApsxdxLUpPEb9lYmp1LvmnvhnH8Ajh9zalAk0KJh ktOpeF7R3LJjhpG1LMcYSNZJzjcYNyenYE1o5rH2yRGcG0ryvigKyMXllN6uZpquAFTH 4nYGpTjAGdBqMEcywQoii2+ItY7oPZ7Wp4JXI2qecNOAsod/W8G8DGSuzlbhGok5bIfH WH/A== X-Gm-Message-State: AMke39lRqPFi5sZP0biy9GXWhfJdiCOWucti2ujeAKoM1BStWFK9uaSIZXp6Q6HTOLjzsQ== X-Received: by 10.28.173.140 with SMTP id w134mr8860989wme.56.1486764617010; Fri, 10 Feb 2017 14:10:17 -0800 (PST) Received: from mail.broadcom.com ([192.19.218.250]) by smtp.gmail.com with ESMTPSA id u184sm1251473wmb.29.2017.02.10.14.10.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 10 Feb 2017 14:10:16 -0800 (PST) From: Kamal Dasu To: linux-spi@vger.kernel.org, cyrille.pitchen@atmel.com, marex@denx.de, broonie@kernel.org Cc: linux-mtd@lists.infradead.org, f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, Kamal Dasu Subject: [PATCH v3 1/2] mtd: spi-nor: Added spi-nor reset function Date: Fri, 10 Feb 2017 16:49:28 -0500 Message-Id: <1486763369-31969-2-git-send-email-kdasu.kdev@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1486763369-31969-1-git-send-email-kdasu.kdev@gmail.com> References: <1486763369-31969-1-git-send-email-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Refactored spi_nor_scan() code to add spi_nor_init() function that programs the spi-nor flash to: 1) remove flash protection if applicable 2) set read mode to quad mode if configured such 3) set the address width based on the flash size and vendor On pm resume spi-nor flash may need to be reconfigured after power reset, there is no need to go through a full spi_nor_scan(), flash device driver needs to call spi_nor_reset() to reprogram the flash to its probed state. Signed-off-by: Kamal Dasu Conflicts: drivers/mtd/spi-nor/spi-nor.c --- drivers/mtd/spi-nor/spi-nor.c | 72 +++++++++++++++++++++++++++---------------- include/linux/mtd/spi-nor.h | 21 ++++++++++++- 2 files changed, 65 insertions(+), 28 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 70e52ff..2bf7f4f 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1526,6 +1526,44 @@ static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor) return 0; } +int spi_nor_init(struct spi_nor *nor) +{ + int ret = 0; + const struct flash_info *info = nor->info; + struct device *dev = nor->dev; + + /* + * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up + * with the software protection bits set + */ + + if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || + JEDEC_MFR(info) == SNOR_MFR_INTEL || + JEDEC_MFR(info) == SNOR_MFR_SST || + info->flags & SPI_NOR_HAS_LOCK) { + write_enable(nor); + write_sr(nor, 0); + spi_nor_wait_till_ready(nor); + } + + if (nor->flash_read == SPI_NOR_QUAD) { + ret = set_quad_mode(nor, info); + if (ret) { + dev_err(dev, "quad mode not supported\n"); + return ret; + } + } + + if (JEDEC_MFR(info) == SNOR_MFR_SPANSION || + info->flags & SPI_NOR_4B_OPCODES) + spi_nor_set_4byte_opcodes(nor, info); + else + set_4byte(nor, info, 1); + + return ret; +} +EXPORT_SYMBOL_GPL(spi_nor_init); + int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) { const struct flash_info *info = NULL; @@ -1571,6 +1609,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) } } + nor->info = info; mutex_init(&nor->lock); /* @@ -1581,20 +1620,6 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) if (info->flags & SPI_S3AN) nor->flags |= SNOR_F_READY_XSR_RDY; - /* - * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up - * with the software protection bits set - */ - - if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || - JEDEC_MFR(info) == SNOR_MFR_INTEL || - JEDEC_MFR(info) == SNOR_MFR_SST || - info->flags & SPI_NOR_HAS_LOCK) { - write_enable(nor); - write_sr(nor, 0); - spi_nor_wait_till_ready(nor); - } - if (!mtd->name) mtd->name = dev_name(dev); mtd->priv = nor; @@ -1669,11 +1694,6 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) /* Quad/Dual-read mode takes precedence over fast/normal */ if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) { - ret = set_quad_mode(nor, info); - if (ret) { - dev_err(dev, "quad mode not supported\n"); - return ret; - } nor->flash_read = SPI_NOR_QUAD; } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) { nor->flash_read = SPI_NOR_DUAL; @@ -1702,17 +1722,11 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) if (info->addr_width) nor->addr_width = info->addr_width; - else if (mtd->size > 0x1000000) { + else if (mtd->size > 0x1000000) /* enable 4-byte addressing if the device exceeds 16MiB */ nor->addr_width = 4; - if (JEDEC_MFR(info) == SNOR_MFR_SPANSION || - info->flags & SPI_NOR_4B_OPCODES) - spi_nor_set_4byte_opcodes(nor, info); - else - set_4byte(nor, info, 1); - } else { + else nor->addr_width = 3; - } if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { dev_err(dev, "address width is too large: %u\n", @@ -1728,6 +1742,10 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) return ret; } + ret = spi_nor_init(nor); + if (ret) + return ret; + dev_info(dev, "%s (%lld Kbytes)\n", info->name, (long long)mtd->size >> 10); diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index f2a7180..945b4d4 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -143,6 +143,8 @@ enum spi_nor_option_flags { SNOR_F_READY_XSR_RDY = BIT(4), }; +struct flash_info; + /** * struct spi_nor - Structure for defining a the SPI NOR layer * @mtd: point to a mtd_info structure @@ -176,6 +178,7 @@ enum spi_nor_option_flags { * @priv: the private data */ struct spi_nor { + const struct flash_info *info; struct mtd_info mtd; struct mutex lock; struct device *dev; @@ -220,12 +223,28 @@ static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor) } /** + * spi_nor_init() - reset scan the SPI NOR + * @nor: the spi_nor structure + * + * The drivers uses this function to initialize the SPI NOR flash device to + * its scanned state, it shall use all nor information set on poweron + * for the read mode, address width and remove protection for certain spi-nor + * manufacturers. This would be needed to be called for flash devices that are + * reset during power management. + * + * The chip type name can be provided through the @name parameter. + * + * Return: 0 for success, others for failure. + */ +int spi_nor_init(struct spi_nor *nor); + +/** * spi_nor_scan() - scan the SPI NOR * @nor: the spi_nor structure * @name: the chip type name * @mode: the read mode supported by the driver * - * The drivers can use this fuction to scan the SPI NOR. + * The drivers can use this function to scan the SPI NOR. * In the scanning, it will try to get all the necessary information to * fill the mtd_info{} and the spi_nor{}. *