From patchwork Tue Feb 14 15:32:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 9572139 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5B58760578 for ; Tue, 14 Feb 2017 15:33:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4F7E120242 for ; Tue, 14 Feb 2017 15:33:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 440DA28417; Tue, 14 Feb 2017 15:33:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B011428408 for ; Tue, 14 Feb 2017 15:33:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754081AbdBNPdG (ORCPT ); Tue, 14 Feb 2017 10:33:06 -0500 Received: from mail-ot0-f196.google.com ([74.125.82.196]:36515 "EHLO mail-ot0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752244AbdBNPdF (ORCPT ); Tue, 14 Feb 2017 10:33:05 -0500 Received: by mail-ot0-f196.google.com with SMTP id l26so3827144ota.3 for ; Tue, 14 Feb 2017 07:33:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EaKstI8BHDP89hQuSUZwi78FqD3nQthgjZimCflC5Jo=; b=YhdcDUXGSLOdXxzUXGDOTKcqvyLDHmR//VV/1iNxwdjIz33Yr+qQDtdQKITdKDfv5V MUqjfc6gtMrnrMPWDUz1qt6y9cRGn2XRaEF0IKR/Nux05lSMF4WZXoVG2TD2lNyLGkyG fS+e36hRGlkG5KZji9xX8FAE2YELSCR8vXIX9yyclNeYH8jVG+pq6d/dtbg29JNR6mko +0fVBV9wWp4tYAp5aNCv2OwY7LSmUA5XTNLLwDh9f/h2cqlyrwbiQhZ1XLnJGQiwz9Yn kxVQhXL/vur0yQ1jhfO2Z929yb7wha4h3qMg9ctO959IpStyAIWLlTIhdoVAGq0D+BPt CRWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EaKstI8BHDP89hQuSUZwi78FqD3nQthgjZimCflC5Jo=; b=C3D5PpWAzvJL++N1k3m1SRYLu1nOiXRiL6BooP0jpPjColy9HoxE6WZsVUfbHubYZ4 x6kBBuszHemeplWMqUlSRB1o6jabuyAa+quuuEjV+8XNFxyLjiDrcrEhXRW9n9beTITe uK9l95RgbwjPR5+qz4xXtcDNBrcF1m4qzORU3T3lyq4AWMz5gyI4/QDpJfo+DY+FqDwp cemqTUxk6eDbd6NrQm7Fp+RX/UHrhZ4dHnUiGcN8iYQ9TOYkgS2hcfZILf/mzNtEMUHi KxBfhad4sOaCDAhchsHmt3/hwsnGAnXMtpmmVGsOO37zL5qepXuqU0JqkJ+ZAMDSPaw+ 07Tw== X-Gm-Message-State: AMke39kUt/7xVnysifanBAoWjDiYBD0a7p9Fs+FTreK1FtrQyuBqbyKC6lfAceQXe/Iakg== X-Received: by 10.99.121.195 with SMTP id u186mr33325626pgc.96.1487086379625; Tue, 14 Feb 2017 07:32:59 -0800 (PST) Received: from mail.broadcom.com ([192.19.224.250]) by smtp.gmail.com with ESMTPSA id a2sm2059794pfc.72.2017.02.14.07.32.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 14 Feb 2017 07:32:59 -0800 (PST) From: Kamal Dasu To: linux-spi@vger.kernel.org, cyrille.pitchen@atmel.com, marex@denx.de, broonie@kernel.org Cc: linux-mtd@lists.infradead.org, f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, Kamal Dasu Subject: [PATCH v4 1/2] mtd: spi-nor: Added spi-nor init function Date: Tue, 14 Feb 2017 10:32:47 -0500 Message-Id: <1487086368-4118-2-git-send-email-kdasu.kdev@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1487086368-4118-1-git-send-email-kdasu.kdev@gmail.com> References: <1487086368-4118-1-git-send-email-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Refactored spi_nor_scan() code to add spi_nor_init() function that programs the spi-nor flash to: 1) remove flash protection if applicable 2) set read mode to quad mode if configured such 3) set the address width based on the flash size and vendor spi_nor_scan() now calls spi_nor_init() to setup nor flash. Signed-off-by: Kamal Dasu --- drivers/mtd/spi-nor/spi-nor.c | 72 +++++++++++++++++++++++++++---------------- include/linux/mtd/spi-nor.h | 18 ++++++++++- 2 files changed, 62 insertions(+), 28 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 70e52ff..2bf7f4f 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1526,6 +1526,44 @@ static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor) return 0; } +int spi_nor_init(struct spi_nor *nor) +{ + int ret = 0; + const struct flash_info *info = nor->info; + struct device *dev = nor->dev; + + /* + * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up + * with the software protection bits set + */ + + if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || + JEDEC_MFR(info) == SNOR_MFR_INTEL || + JEDEC_MFR(info) == SNOR_MFR_SST || + info->flags & SPI_NOR_HAS_LOCK) { + write_enable(nor); + write_sr(nor, 0); + spi_nor_wait_till_ready(nor); + } + + if (nor->flash_read == SPI_NOR_QUAD) { + ret = set_quad_mode(nor, info); + if (ret) { + dev_err(dev, "quad mode not supported\n"); + return ret; + } + } + + if (JEDEC_MFR(info) == SNOR_MFR_SPANSION || + info->flags & SPI_NOR_4B_OPCODES) + spi_nor_set_4byte_opcodes(nor, info); + else + set_4byte(nor, info, 1); + + return ret; +} +EXPORT_SYMBOL_GPL(spi_nor_init); + int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) { const struct flash_info *info = NULL; @@ -1571,6 +1609,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) } } + nor->info = info; mutex_init(&nor->lock); /* @@ -1581,20 +1620,6 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) if (info->flags & SPI_S3AN) nor->flags |= SNOR_F_READY_XSR_RDY; - /* - * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up - * with the software protection bits set - */ - - if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || - JEDEC_MFR(info) == SNOR_MFR_INTEL || - JEDEC_MFR(info) == SNOR_MFR_SST || - info->flags & SPI_NOR_HAS_LOCK) { - write_enable(nor); - write_sr(nor, 0); - spi_nor_wait_till_ready(nor); - } - if (!mtd->name) mtd->name = dev_name(dev); mtd->priv = nor; @@ -1669,11 +1694,6 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) /* Quad/Dual-read mode takes precedence over fast/normal */ if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) { - ret = set_quad_mode(nor, info); - if (ret) { - dev_err(dev, "quad mode not supported\n"); - return ret; - } nor->flash_read = SPI_NOR_QUAD; } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) { nor->flash_read = SPI_NOR_DUAL; @@ -1702,17 +1722,11 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) if (info->addr_width) nor->addr_width = info->addr_width; - else if (mtd->size > 0x1000000) { + else if (mtd->size > 0x1000000) /* enable 4-byte addressing if the device exceeds 16MiB */ nor->addr_width = 4; - if (JEDEC_MFR(info) == SNOR_MFR_SPANSION || - info->flags & SPI_NOR_4B_OPCODES) - spi_nor_set_4byte_opcodes(nor, info); - else - set_4byte(nor, info, 1); - } else { + else nor->addr_width = 3; - } if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { dev_err(dev, "address width is too large: %u\n", @@ -1728,6 +1742,10 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) return ret; } + ret = spi_nor_init(nor); + if (ret) + return ret; + dev_info(dev, "%s (%lld Kbytes)\n", info->name, (long long)mtd->size >> 10); diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index f2a7180..29a8283 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -143,6 +143,8 @@ enum spi_nor_option_flags { SNOR_F_READY_XSR_RDY = BIT(4), }; +struct flash_info; + /** * struct spi_nor - Structure for defining a the SPI NOR layer * @mtd: point to a mtd_info structure @@ -174,6 +176,7 @@ enum spi_nor_option_flags { * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is * completely locked * @priv: the private data + * @info: points to the flash_info structure */ struct spi_nor { struct mtd_info mtd; @@ -206,6 +209,7 @@ struct spi_nor { int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); void *priv; + const struct flash_info *info; }; static inline void spi_nor_set_flash_node(struct spi_nor *nor, @@ -220,12 +224,24 @@ static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor) } /** + * spi_nor_init() - initialize SPI NOR + * @nor: the spi_nor structure + * + * The drivers uses this function to initialize the SPI NOR flash device to + * settings in spi_nor structure. The functions sets read mode, address width + * and removes protection on the flash device based on those settings. + * + * Return: 0 for success, others for failure. + */ +int spi_nor_init(struct spi_nor *nor); + +/** * spi_nor_scan() - scan the SPI NOR * @nor: the spi_nor structure * @name: the chip type name * @mode: the read mode supported by the driver * - * The drivers can use this fuction to scan the SPI NOR. + * The drivers can use this function to scan the SPI NOR. * In the scanning, it will try to get all the necessary information to * fill the mtd_info{} and the spi_nor{}. *