From patchwork Wed Jun 21 14:32:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amelie Delaunay X-Patchwork-Id: 9802003 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D212C6038C for ; Wed, 21 Jun 2017 14:33:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C187A285C9 for ; Wed, 21 Jun 2017 14:33:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B5C0E285CF; Wed, 21 Jun 2017 14:33:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 51650285C9 for ; Wed, 21 Jun 2017 14:33:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752675AbdFUOdF (ORCPT ); Wed, 21 Jun 2017 10:33:05 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:33155 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751806AbdFUOdE (ORCPT ); Wed, 21 Jun 2017 10:33:04 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v5LEVCmd019541; Wed, 21 Jun 2017 16:32:22 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-.pphosted.com with ESMTP id 2b7ket38bb-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 21 Jun 2017 16:32:22 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 7E54434; Wed, 21 Jun 2017 14:32:21 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 6402425A0; Wed, 21 Jun 2017 14:32:21 +0000 (GMT) Received: from localhost (10.201.23.160) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.339.0; Wed, 21 Jun 2017 16:32:21 +0200 From: Amelie Delaunay To: Mark Brown , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue CC: , , , , Amelie Delaunay Subject: [PATCH 1/2] dt-bindings: spi: Document the STM32 SPI bindings Date: Wed, 21 Jun 2017 16:32:05 +0200 Message-ID: <1498055526-6918-2-git-send-email-amelie.delaunay@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498055526-6918-1-git-send-email-amelie.delaunay@st.com> References: <1498055526-6918-1-git-send-email-amelie.delaunay@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.160] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-06-21_03:, , signatures=0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the documentation of device tree bindings for the STM32 SPI controller. Signed-off-by: Amelie Delaunay --- .../devicetree/bindings/spi/spi-stm32.txt | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-stm32.txt diff --git a/Documentation/devicetree/bindings/spi/spi-stm32.txt b/Documentation/devicetree/bindings/spi/spi-stm32.txt new file mode 100644 index 0000000..3958bf6 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-stm32.txt @@ -0,0 +1,60 @@ +STMicroelectronics STM32 SPI Controller + +The STM32 SPI controller is used to communicate with external devices using +the Serial Peripheral Interface. It supports full-duplex, half-duplex and +simplex synchronous serial communication with external devices. It supports +from 4 to 32-bit data size. Although it can be configured as master or slave, +only master is supported by the driver. + +Required properties: +- compatible: Must be "st,stm32-spi". +- reg: Offset and length of the device's register set. +- interrupts: Must contain the interrupt id. +- clocks: Must contain an entry for spiclk (which feeds the internal clock + generator). +- #address-cells: Number of cells required to define a chip select address. +- #size-cells: Should be zero. + +Optional properties: +- resets: Must contain the phandle to the reset controller. +- A pinctrl state named "default" may be defined to set pins in mode of + operation for SPI transfer. +- dmas: DMA specifiers for tx and rx dma. DMA fifo mode must be used. See the + STM32 DMA bindings, Documentation/devicetree/bindings/dma/stm32-dma.txt. +- dma-names: DMA request names should include "tx" and "rx" if present. +- cs-gpios: list of GPIO chip selects. See the SPI bus bindings, + Documentation/devicetree/bindings/spi/spi-bus.txt + + +Child nodes represent devices on the SPI bus + See ../spi/spi-bus.txt + +Optional properties: +- st,spi-midi-ns: (Master Inter-Data Idleness) minimum time delay in + nanoseconds inserted between two consecutive data frames. + + +Example: + spi2: spi@40003800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-spi"; + reg = <0x40003800 0x400>; + interrupts = <36>; + clocks = <&rcc SPI2_CK>; + resets = <&rcc 1166>; + dmas = <&dmamux1 0 39 0x400 0x01>, + <&dmamux1 1 40 0x400 0x01>; + dma-names = "rx", "tx"; + pinctrl-0 = <&spi2_pins_b>; + pinctrl-names = "default"; + status = "okay"; + cs-gpios = <&gpioa 11 0>; + + spidev@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <4000000>; + st,spi-midi = <4000>; + }; + };