From patchwork Tue Jun 27 15:45:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amelie Delaunay X-Patchwork-Id: 9812705 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6654560351 for ; Tue, 27 Jun 2017 15:48:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 582DC28696 for ; Tue, 27 Jun 2017 15:48:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4CF48286E1; Tue, 27 Jun 2017 15:48:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F18CC28696 for ; Tue, 27 Jun 2017 15:48:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751888AbdF0Prn (ORCPT ); Tue, 27 Jun 2017 11:47:43 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:38493 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751804AbdF0PqK (ORCPT ); Tue, 27 Jun 2017 11:46:10 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v5RFi4tF007655; Tue, 27 Jun 2017 17:45:37 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-.pphosted.com with ESMTP id 2battv0d7a-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 27 Jun 2017 17:45:37 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 6438531; Tue, 27 Jun 2017 15:45:36 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 431DB2572; Tue, 27 Jun 2017 15:45:36 +0000 (GMT) Received: from localhost (10.201.23.160) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.339.0; Tue, 27 Jun 2017 17:45:36 +0200 From: Amelie Delaunay To: Mark Brown , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue CC: , , , , Amelie Delaunay Subject: [PATCHv2 1/9] dt-bindings: spi: stm32: use SoC specific compatible Date: Tue, 27 Jun 2017 17:45:13 +0200 Message-ID: <1498578321-13980-2-git-send-email-amelie.delaunay@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498578321-13980-1-git-send-email-amelie.delaunay@st.com> References: <1498578321-13980-1-git-send-email-amelie.delaunay@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.160] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-06-27_09:, , signatures=0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch replaces st,stm32-spi compatible with st,stm32h7-spi SoC specific compatible and updates the example accondingly. Signed-off-by: Amelie Delaunay Acked-by: Rob Herring --- Documentation/devicetree/bindings/spi/spi-stm32.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/spi-stm32.txt b/Documentation/devicetree/bindings/spi/spi-stm32.txt index 3958bf6..415378b 100644 --- a/Documentation/devicetree/bindings/spi/spi-stm32.txt +++ b/Documentation/devicetree/bindings/spi/spi-stm32.txt @@ -7,7 +7,7 @@ from 4 to 32-bit data size. Although it can be configured as master or slave, only master is supported by the driver. Required properties: -- compatible: Must be "st,stm32-spi". +- compatible: Must be "st,stm32h7-spi". - reg: Offset and length of the device's register set. - interrupts: Must contain the interrupt id. - clocks: Must contain an entry for spiclk (which feeds the internal clock @@ -38,7 +38,7 @@ Example: spi2: spi@40003800 { #address-cells = <1>; #size-cells = <0>; - compatible = "st,stm32-spi"; + compatible = "st,stm32h7-spi"; reg = <0x40003800 0x400>; interrupts = <36>; clocks = <&rcc SPI2_CK>;