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Wed, 19 Sep 2018 04:52:11 +0000 From: Yogesh Gaur To: linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org Cc: marek.vasut@gmail.com, cyrille.pitchen@wedev4u.fr, boris.brezillon@bootlin.com, computersforpeace@gmail.com, frieder.schrempf@exceet.de, linux-kernel@vger.kernel.org, Yogesh Gaur Subject: [RESEND PATCH 2/2] mtd: spi-nor: add entry for mt35xu512aba flash Date: Wed, 19 Sep 2018 10:20:08 +0530 Message-Id: <1537332608-19561-3-git-send-email-yogeshnarayan.gaur@nxp.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1537332608-19561-1-git-send-email-yogeshnarayan.gaur@nxp.com> References: <1537332608-19561-1-git-send-email-yogeshnarayan.gaur@nxp.com> MIME-Version: 1.0 X-Originating-IP: [14.143.30.134] X-ClientProxiedBy: SG2PR04CA0173.apcprd04.prod.outlook.com (2603:1096:4::35) To HE1PR04MB1034.eurprd04.prod.outlook.com (2a01:111:e400:581a::15) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 174d42b5-f866-4da5-7c89-08d61debab98 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(7020095)(4652040)(8989299)(4534165)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020);SRVR:HE1PR04MB1034; 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This flash is having uniform sector erase size of 128KB, have support of FSR(flag status register), flash size is 64MB and supports 4-byte commands. Signed-off-by: Yogesh Gaur --- drivers/mtd/spi-nor/spi-nor.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 33a55bc..6042df8 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1113,6 +1113,9 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, + /* Micron */ + { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512, SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES) }, + /* PMC */ { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) }, { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },