diff mbox series

[v3,1/2] mtd: spi-nor: add macros related to MICRON flash

Message ID 1539310881-17438-2-git-send-email-yogeshnarayan.gaur@nxp.com (mailing list archive)
State Accepted
Commit 0005aad094538e1c290b1cdb5b940e4a16f405b0
Headers show
Series mtd: spi-nor: add entry for mt35xu512aba flash | expand

Commit Message

Yogesh Narayan Gaur Oct. 12, 2018, 2:23 a.m. UTC 
Some MICRON related macros in spi-nor domain were ST.
Rename entries related to STMicroelectronics under macro SNOR_MFR_ST.

Added entry of MFR Id for Micron flashes, 0x002C.

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
Changes for v3:
- None
Changes for v2:
- None

 drivers/mtd/spi-nor/spi-nor.c | 9 ++++++---
 include/linux/mtd/cfi.h       | 1 +
 include/linux/mtd/spi-nor.h   | 3 ++-
 3 files changed, 9 insertions(+), 4 deletions(-)

Comments

Boris Brezillon Oct. 12, 2018, 6:07 a.m. UTC | #1 
On Fri, 12 Oct 2018 02:23:08 +0000
Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> wrote:

> Some MICRON related macros in spi-nor domain were ST.
> Rename entries related to STMicroelectronics under macro SNOR_MFR_ST.
> 
> Added entry of MFR Id for Micron flashes, 0x002C.
> 
> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> ---
> Changes for v3:
> - None
> Changes for v2:
> - None
> 
>  drivers/mtd/spi-nor/spi-nor.c | 9 ++++++---
>  include/linux/mtd/cfi.h       | 1 +
>  include/linux/mtd/spi-nor.h   | 3 ++-
>  3 files changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 9407ca5..b8b494f 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -284,6 +284,7 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
>  	u8 cmd;
>  
>  	switch (JEDEC_MFR(info)) {
> +	case SNOR_MFR_ST:
>  	case SNOR_MFR_MICRON:
>  		/* Some Micron need WREN command; all will accept it */
>  		need_wren = true;
> @@ -1388,7 +1389,7 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
>  	{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>  	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
>  
> -	/* Micron */
> +	/* Micron <--> ST Micro */
>  	{ "n25q016a",	 INFO(0x20bb15, 0, 64 * 1024,   32, SECT_4K | SPI_NOR_QUAD_READ) },
>  	{ "n25q032",	 INFO(0x20ba16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) },
>  	{ "n25q032a",	 INFO(0x20bb16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) },
> @@ -3223,6 +3224,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
>  			params->quad_enable = macronix_quad_enable;
>  			break;
>  
> +		case SNOR_MFR_ST:
>  		case SNOR_MFR_MICRON:
>  			break;
>  
> @@ -3671,8 +3673,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
>  	mtd->_resume = spi_nor_resume;
>  
>  	/* NOR protection support for STmicro/Micron chips and similar */
> -	if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
> -			info->flags & SPI_NOR_HAS_LOCK) {
> +	if (JEDEC_MFR(info) == SNOR_MFR_ST ||
> +	    JEDEC_MFR(info) == SNOR_MFR_MICRON ||
> +	    info->flags & SPI_NOR_HAS_LOCK) {
>  		nor->flash_lock = stm_lock;
>  		nor->flash_unlock = stm_unlock;
>  		nor->flash_is_locked = stm_is_locked;

Are you sure ST and Micron NORs work the same way WRT locking, 4-byte
addressing mode and Quad enable?

> diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h
> index 9b57a9b..cbf7716 100644
> --- a/include/linux/mtd/cfi.h
> +++ b/include/linux/mtd/cfi.h
> @@ -377,6 +377,7 @@ struct cfi_fixup {
>  #define CFI_MFR_SHARP		0x00B0
>  #define CFI_MFR_SST		0x00BF
>  #define CFI_MFR_ST		0x0020 /* STMicroelectronics */
> +#define CFI_MFR_MICRON		0x002C /* Micron */
>  #define CFI_MFR_TOSHIBA		0x0098
>  #define CFI_MFR_WINBOND		0x00DA
>  
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index 7f0c730..8b1acf6 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -23,7 +23,8 @@
>  #define SNOR_MFR_ATMEL		CFI_MFR_ATMEL
>  #define SNOR_MFR_GIGADEVICE	0xc8
>  #define SNOR_MFR_INTEL		CFI_MFR_INTEL
> -#define SNOR_MFR_MICRON		CFI_MFR_ST /* ST Micro <--> Micron */
> +#define SNOR_MFR_ST		CFI_MFR_ST	/* ST Micro */
> +#define SNOR_MFR_MICRON		CFI_MFR_MICRON	/* Micron */
>  #define SNOR_MFR_MACRONIX	CFI_MFR_MACRONIX
>  #define SNOR_MFR_SPANSION	CFI_MFR_AMD
>  #define SNOR_MFR_SST		CFI_MFR_SST
Yogesh Narayan Gaur Oct. 12, 2018, 6:31 a.m. UTC | #2 
Hi Boris,

> -----Original Message-----
> From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> Sent: Friday, October 12, 2018 11:38 AM
> To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
> Cc: linux-mtd@lists.infradead.org; linux-spi@vger.kernel.org;
> tudor.ambarus@microchip.com; marek.vasut@gmail.com;
> cyrille.pitchen@wedev4u.fr; computersforpeace@gmail.com;
> frieder.schrempf@exceet.de; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON flash
> 
> On Fri, 12 Oct 2018 02:23:08 +0000
> Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> wrote:
> 
> > Some MICRON related macros in spi-nor domain were ST.
> > Rename entries related to STMicroelectronics under macro SNOR_MFR_ST.
> >
> > Added entry of MFR Id for Micron flashes, 0x002C.
> >
> > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> > ---
> > Changes for v3:
> > - None
> > Changes for v2:
> > - None
> >
> >  drivers/mtd/spi-nor/spi-nor.c | 9 ++++++---
> >  include/linux/mtd/cfi.h       | 1 +
> >  include/linux/mtd/spi-nor.h   | 3 ++-
> >  3 files changed, 9 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c
> > b/drivers/mtd/spi-nor/spi-nor.c index 9407ca5..b8b494f 100644
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -284,6 +284,7 @@ static inline int set_4byte(struct spi_nor *nor, const
> struct flash_info *info,
> >  	u8 cmd;
> >
> >  	switch (JEDEC_MFR(info)) {
> > +	case SNOR_MFR_ST:
> >  	case SNOR_MFR_MICRON:
> >  		/* Some Micron need WREN command; all will accept it */
> >  		need_wren = true;
> > @@ -1388,7 +1389,7 @@ static int spi_nor_is_locked(struct mtd_info *mtd,
> loff_t ofs, uint64_t len)
> >  	{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> >  	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048,
> > SPI_NOR_QUAD_READ) },
> >
> > -	/* Micron */
> > +	/* Micron <--> ST Micro */
> >  	{ "n25q016a",	 INFO(0x20bb15, 0, 64 * 1024,   32, SECT_4K |
> SPI_NOR_QUAD_READ) },
> >  	{ "n25q032",	 INFO(0x20ba16, 0, 64 * 1024,   64,
> SPI_NOR_QUAD_READ) },
> >  	{ "n25q032a",	 INFO(0x20bb16, 0, 64 * 1024,   64,
> SPI_NOR_QUAD_READ) },
> > @@ -3223,6 +3224,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
> >  			params->quad_enable = macronix_quad_enable;
> >  			break;
> >
> > +		case SNOR_MFR_ST:
> >  		case SNOR_MFR_MICRON:
> >  			break;
> >
> > @@ -3671,8 +3673,9 @@ int spi_nor_scan(struct spi_nor *nor, const char
> *name,
> >  	mtd->_resume = spi_nor_resume;
> >
> >  	/* NOR protection support for STmicro/Micron chips and similar */
> > -	if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
> > -			info->flags & SPI_NOR_HAS_LOCK) {
> > +	if (JEDEC_MFR(info) == SNOR_MFR_ST ||
> > +	    JEDEC_MFR(info) == SNOR_MFR_MICRON ||
> > +	    info->flags & SPI_NOR_HAS_LOCK) {
> >  		nor->flash_lock = stm_lock;
> >  		nor->flash_unlock = stm_unlock;
> >  		nor->flash_is_locked = stm_is_locked;
> 
> Are you sure ST and Micron NORs work the same way WRT locking, 4-byte
> addressing mode and Quad enable?

Have checked for the Micron flash, MT35x wrt locking, 4-byte addressing mode.
For Macronix and Spansion flash there is special handling required for quad mode but not needed for ST flash.
This flash didn't support quad mode and have checked that other Micron flash also didn't need special handling for quad mode.
--
Regards
Yogesh Gaur.
> 
> > diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h index
> > 9b57a9b..cbf7716 100644
> > --- a/include/linux/mtd/cfi.h
> > +++ b/include/linux/mtd/cfi.h
> > @@ -377,6 +377,7 @@ struct cfi_fixup {
> >  #define CFI_MFR_SHARP		0x00B0
> >  #define CFI_MFR_SST		0x00BF
> >  #define CFI_MFR_ST		0x0020 /* STMicroelectronics */
> > +#define CFI_MFR_MICRON		0x002C /* Micron */
> >  #define CFI_MFR_TOSHIBA		0x0098
> >  #define CFI_MFR_WINBOND		0x00DA
> >
> > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> > index 7f0c730..8b1acf6 100644
> > --- a/include/linux/mtd/spi-nor.h
> > +++ b/include/linux/mtd/spi-nor.h
> > @@ -23,7 +23,8 @@
> >  #define SNOR_MFR_ATMEL		CFI_MFR_ATMEL
> >  #define SNOR_MFR_GIGADEVICE	0xc8
> >  #define SNOR_MFR_INTEL		CFI_MFR_INTEL
> > -#define SNOR_MFR_MICRON		CFI_MFR_ST /* ST Micro <--> Micron
> */
> > +#define SNOR_MFR_ST		CFI_MFR_ST	/* ST Micro */
> > +#define SNOR_MFR_MICRON		CFI_MFR_MICRON	/* Micron */
> >  #define SNOR_MFR_MACRONIX	CFI_MFR_MACRONIX
> >  #define SNOR_MFR_SPANSION	CFI_MFR_AMD
> >  #define SNOR_MFR_SST		CFI_MFR_SST
Yogesh Narayan Gaur Oct. 23, 2018, 9:39 a.m. UTC | #3 
Hi,

Did we have have any comments or remarks about this patch-series,  if not please apply.

Both patches in the series been reviewed by Tudor.

--
Regards
Yogesh Gaur

> -----Original Message-----
> From: Yogesh Narayan Gaur
> Sent: Friday, October 12, 2018 12:02 PM
> To: 'Boris Brezillon' <boris.brezillon@bootlin.com>
> Cc: linux-mtd@lists.infradead.org; linux-spi@vger.kernel.org;
> tudor.ambarus@microchip.com; marek.vasut@gmail.com;
> cyrille.pitchen@wedev4u.fr; computersforpeace@gmail.com;
> frieder.schrempf@exceet.de; linux-kernel@vger.kernel.org
> Subject: RE: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON flash
> 
> Hi Boris,
> 
> > -----Original Message-----
> > From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> > Sent: Friday, October 12, 2018 11:38 AM
> > To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
> > Cc: linux-mtd@lists.infradead.org; linux-spi@vger.kernel.org;
> > tudor.ambarus@microchip.com; marek.vasut@gmail.com;
> > cyrille.pitchen@wedev4u.fr; computersforpeace@gmail.com;
> > frieder.schrempf@exceet.de; linux-kernel@vger.kernel.org
> > Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON
> > flash
> >
> > On Fri, 12 Oct 2018 02:23:08 +0000
> > Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> wrote:
> >
> > > Some MICRON related macros in spi-nor domain were ST.
> > > Rename entries related to STMicroelectronics under macro SNOR_MFR_ST.
> > >
> > > Added entry of MFR Id for Micron flashes, 0x002C.
> > >
> > > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > > Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> > > ---
> > > Changes for v3:
> > > - None
> > > Changes for v2:
> > > - None
> > >
> > >  drivers/mtd/spi-nor/spi-nor.c | 9 ++++++---
> > >  include/linux/mtd/cfi.h       | 1 +
> > >  include/linux/mtd/spi-nor.h   | 3 ++-
> > >  3 files changed, 9 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/mtd/spi-nor/spi-nor.c
> > > b/drivers/mtd/spi-nor/spi-nor.c index 9407ca5..b8b494f 100644
> > > --- a/drivers/mtd/spi-nor/spi-nor.c
> > > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > > @@ -284,6 +284,7 @@ static inline int set_4byte(struct spi_nor *nor,
> > > const
> > struct flash_info *info,
> > >  	u8 cmd;
> > >
> > >  	switch (JEDEC_MFR(info)) {
> > > +	case SNOR_MFR_ST:
> > >  	case SNOR_MFR_MICRON:
> > >  		/* Some Micron need WREN command; all will accept it */
> > >  		need_wren = true;
> > > @@ -1388,7 +1389,7 @@ static int spi_nor_is_locked(struct mtd_info
> > > *mtd,
> > loff_t ofs, uint64_t len)
> > >  	{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K |
> > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> > >  	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048,
> > > SPI_NOR_QUAD_READ) },
> > >
> > > -	/* Micron */
> > > +	/* Micron <--> ST Micro */
> > >  	{ "n25q016a",	 INFO(0x20bb15, 0, 64 * 1024,   32, SECT_4K |
> > SPI_NOR_QUAD_READ) },
> > >  	{ "n25q032",	 INFO(0x20ba16, 0, 64 * 1024,   64,
> > SPI_NOR_QUAD_READ) },
> > >  	{ "n25q032a",	 INFO(0x20bb16, 0, 64 * 1024,   64,
> > SPI_NOR_QUAD_READ) },
> > > @@ -3223,6 +3224,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
> > >  			params->quad_enable = macronix_quad_enable;
> > >  			break;
> > >
> > > +		case SNOR_MFR_ST:
> > >  		case SNOR_MFR_MICRON:
> > >  			break;
> > >
> > > @@ -3671,8 +3673,9 @@ int spi_nor_scan(struct spi_nor *nor, const
> > > char
> > *name,
> > >  	mtd->_resume = spi_nor_resume;
> > >
> > >  	/* NOR protection support for STmicro/Micron chips and similar */
> > > -	if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
> > > -			info->flags & SPI_NOR_HAS_LOCK) {
> > > +	if (JEDEC_MFR(info) == SNOR_MFR_ST ||
> > > +	    JEDEC_MFR(info) == SNOR_MFR_MICRON ||
> > > +	    info->flags & SPI_NOR_HAS_LOCK) {
> > >  		nor->flash_lock = stm_lock;
> > >  		nor->flash_unlock = stm_unlock;
> > >  		nor->flash_is_locked = stm_is_locked;
> >
> > Are you sure ST and Micron NORs work the same way WRT locking, 4-byte
> > addressing mode and Quad enable?
> 
> Have checked for the Micron flash, MT35x wrt locking, 4-byte addressing mode.
> For Macronix and Spansion flash there is special handling required for quad
> mode but not needed for ST flash.
> This flash didn't support quad mode and have checked that other Micron flash
> also didn't need special handling for quad mode.
> --
> Regards
> Yogesh Gaur.
> >
> > > diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h index
> > > 9b57a9b..cbf7716 100644
> > > --- a/include/linux/mtd/cfi.h
> > > +++ b/include/linux/mtd/cfi.h
> > > @@ -377,6 +377,7 @@ struct cfi_fixup {
> > >  #define CFI_MFR_SHARP		0x00B0
> > >  #define CFI_MFR_SST		0x00BF
> > >  #define CFI_MFR_ST		0x0020 /* STMicroelectronics */
> > > +#define CFI_MFR_MICRON		0x002C /* Micron */
> > >  #define CFI_MFR_TOSHIBA		0x0098
> > >  #define CFI_MFR_WINBOND		0x00DA
> > >
> > > diff --git a/include/linux/mtd/spi-nor.h
> > > b/include/linux/mtd/spi-nor.h index 7f0c730..8b1acf6 100644
> > > --- a/include/linux/mtd/spi-nor.h
> > > +++ b/include/linux/mtd/spi-nor.h
> > > @@ -23,7 +23,8 @@
> > >  #define SNOR_MFR_ATMEL		CFI_MFR_ATMEL
> > >  #define SNOR_MFR_GIGADEVICE	0xc8
> > >  #define SNOR_MFR_INTEL		CFI_MFR_INTEL
> > > -#define SNOR_MFR_MICRON		CFI_MFR_ST /* ST Micro <-->
> Micron
> > */
> > > +#define SNOR_MFR_ST		CFI_MFR_ST	/* ST Micro */
> > > +#define SNOR_MFR_MICRON		CFI_MFR_MICRON	/*
> Micron */
> > >  #define SNOR_MFR_MACRONIX	CFI_MFR_MACRONIX
> > >  #define SNOR_MFR_SPANSION	CFI_MFR_AMD
> > >  #define SNOR_MFR_SST		CFI_MFR_SST
Boris Brezillon Oct. 23, 2018, 9:56 a.m. UTC | #4 
Hi Yogesh,

On Tue, 23 Oct 2018 09:39:25 +0000
Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> wrote:

> Hi,
> 
> Did we have have any comments or remarks about this patch-series,  if not please apply.

Sorry, but it was already too late for this release, and the merge
window just started, so it will have to wait at least 2 more weeks.

We've been lagging with SPI NOR patches for the last couple releases
because I clearly don't have time to review those contributions, and it
seems Marek does not have time either.

> 
> Both patches in the series been reviewed by Tudor.

Things are improving a bit thanks to Tudor's involvement in the review
process, but I'd like to remember you that you, as a regular
contributor to the spi-nor subsystem, can help us with that too. That
is, help review patches coming from others instead of only focusing on
your own contributions.

Regards,

Boris
Tudor Ambarus Oct. 23, 2018, 9:58 a.m. UTC | #5 
Hi,

On 10/23/2018 12:39 PM, Yogesh Narayan Gaur wrote:
> Hi,
> 
> Did we have have any comments or remarks about this patch-series,  if not please apply.

Now that the octal mode is close to an end, it would make sense to wait for it,
so that you can add the octal flag for this memory when introduced. Of course,
not a show stopper.

Cheers,
ta

> 
> Both patches in the series been reviewed by Tudor.
> 
> --
> Regards
> Yogesh Gaur
> 
>> -----Original Message-----
>> From: Yogesh Narayan Gaur
>> Sent: Friday, October 12, 2018 12:02 PM
>> To: 'Boris Brezillon' <boris.brezillon@bootlin.com>
>> Cc: linux-mtd@lists.infradead.org; linux-spi@vger.kernel.org;
>> tudor.ambarus@microchip.com; marek.vasut@gmail.com;
>> cyrille.pitchen@wedev4u.fr; computersforpeace@gmail.com;
>> frieder.schrempf@exceet.de; linux-kernel@vger.kernel.org
>> Subject: RE: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON flash
>>
>> Hi Boris,
>>
>>> -----Original Message-----
>>> From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
>>> Sent: Friday, October 12, 2018 11:38 AM
>>> To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
>>> Cc: linux-mtd@lists.infradead.org; linux-spi@vger.kernel.org;
>>> tudor.ambarus@microchip.com; marek.vasut@gmail.com;
>>> cyrille.pitchen@wedev4u.fr; computersforpeace@gmail.com;
>>> frieder.schrempf@exceet.de; linux-kernel@vger.kernel.org
>>> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON
>>> flash
>>>
>>> On Fri, 12 Oct 2018 02:23:08 +0000
>>> Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> wrote:
>>>
>>>> Some MICRON related macros in spi-nor domain were ST.
>>>> Rename entries related to STMicroelectronics under macro SNOR_MFR_ST.
>>>>
>>>> Added entry of MFR Id for Micron flashes, 0x002C.
>>>>
>>>> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
>>>> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
>>>> ---
>>>> Changes for v3:
>>>> - None
>>>> Changes for v2:
>>>> - None
>>>>
>>>>  drivers/mtd/spi-nor/spi-nor.c | 9 ++++++---
>>>>  include/linux/mtd/cfi.h       | 1 +
>>>>  include/linux/mtd/spi-nor.h   | 3 ++-
>>>>  3 files changed, 9 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/drivers/mtd/spi-nor/spi-nor.c
>>>> b/drivers/mtd/spi-nor/spi-nor.c index 9407ca5..b8b494f 100644
>>>> --- a/drivers/mtd/spi-nor/spi-nor.c
>>>> +++ b/drivers/mtd/spi-nor/spi-nor.c
>>>> @@ -284,6 +284,7 @@ static inline int set_4byte(struct spi_nor *nor,
>>>> const
>>> struct flash_info *info,
>>>>  	u8 cmd;
>>>>
>>>>  	switch (JEDEC_MFR(info)) {
>>>> +	case SNOR_MFR_ST:
>>>>  	case SNOR_MFR_MICRON:
>>>>  		/* Some Micron need WREN command; all will accept it */
>>>>  		need_wren = true;
>>>> @@ -1388,7 +1389,7 @@ static int spi_nor_is_locked(struct mtd_info
>>>> *mtd,
>>> loff_t ofs, uint64_t len)
>>>>  	{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K |
>>> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>>>>  	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048,
>>>> SPI_NOR_QUAD_READ) },
>>>>
>>>> -	/* Micron */
>>>> +	/* Micron <--> ST Micro */
>>>>  	{ "n25q016a",	 INFO(0x20bb15, 0, 64 * 1024,   32, SECT_4K |
>>> SPI_NOR_QUAD_READ) },
>>>>  	{ "n25q032",	 INFO(0x20ba16, 0, 64 * 1024,   64,
>>> SPI_NOR_QUAD_READ) },
>>>>  	{ "n25q032a",	 INFO(0x20bb16, 0, 64 * 1024,   64,
>>> SPI_NOR_QUAD_READ) },
>>>> @@ -3223,6 +3224,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
>>>>  			params->quad_enable = macronix_quad_enable;
>>>>  			break;
>>>>
>>>> +		case SNOR_MFR_ST:
>>>>  		case SNOR_MFR_MICRON:
>>>>  			break;
>>>>
>>>> @@ -3671,8 +3673,9 @@ int spi_nor_scan(struct spi_nor *nor, const
>>>> char
>>> *name,
>>>>  	mtd->_resume = spi_nor_resume;
>>>>
>>>>  	/* NOR protection support for STmicro/Micron chips and similar */
>>>> -	if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
>>>> -			info->flags & SPI_NOR_HAS_LOCK) {
>>>> +	if (JEDEC_MFR(info) == SNOR_MFR_ST ||
>>>> +	    JEDEC_MFR(info) == SNOR_MFR_MICRON ||
>>>> +	    info->flags & SPI_NOR_HAS_LOCK) {
>>>>  		nor->flash_lock = stm_lock;
>>>>  		nor->flash_unlock = stm_unlock;
>>>>  		nor->flash_is_locked = stm_is_locked;
>>>
>>> Are you sure ST and Micron NORs work the same way WRT locking, 4-byte
>>> addressing mode and Quad enable?
>>
>> Have checked for the Micron flash, MT35x wrt locking, 4-byte addressing mode.
>> For Macronix and Spansion flash there is special handling required for quad
>> mode but not needed for ST flash.
>> This flash didn't support quad mode and have checked that other Micron flash
>> also didn't need special handling for quad mode.
>> --
>> Regards
>> Yogesh Gaur.
>>>
>>>> diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h index
>>>> 9b57a9b..cbf7716 100644
>>>> --- a/include/linux/mtd/cfi.h
>>>> +++ b/include/linux/mtd/cfi.h
>>>> @@ -377,6 +377,7 @@ struct cfi_fixup {
>>>>  #define CFI_MFR_SHARP		0x00B0
>>>>  #define CFI_MFR_SST		0x00BF
>>>>  #define CFI_MFR_ST		0x0020 /* STMicroelectronics */
>>>> +#define CFI_MFR_MICRON		0x002C /* Micron */
>>>>  #define CFI_MFR_TOSHIBA		0x0098
>>>>  #define CFI_MFR_WINBOND		0x00DA
>>>>
>>>> diff --git a/include/linux/mtd/spi-nor.h
>>>> b/include/linux/mtd/spi-nor.h index 7f0c730..8b1acf6 100644
>>>> --- a/include/linux/mtd/spi-nor.h
>>>> +++ b/include/linux/mtd/spi-nor.h
>>>> @@ -23,7 +23,8 @@
>>>>  #define SNOR_MFR_ATMEL		CFI_MFR_ATMEL
>>>>  #define SNOR_MFR_GIGADEVICE	0xc8
>>>>  #define SNOR_MFR_INTEL		CFI_MFR_INTEL
>>>> -#define SNOR_MFR_MICRON		CFI_MFR_ST /* ST Micro <-->
>> Micron
>>> */
>>>> +#define SNOR_MFR_ST		CFI_MFR_ST	/* ST Micro */
>>>> +#define SNOR_MFR_MICRON		CFI_MFR_MICRON	/*
>> Micron */
>>>>  #define SNOR_MFR_MACRONIX	CFI_MFR_MACRONIX
>>>>  #define SNOR_MFR_SPANSION	CFI_MFR_AMD
>>>>  #define SNOR_MFR_SST		CFI_MFR_SST
> 
>
Yogesh Narayan Gaur Oct. 23, 2018, 10 a.m. UTC | #6 
Hi Boris,

> -----Original Message-----
> From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> Sent: Tuesday, October 23, 2018 3:27 PM
> To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
> Cc: Mark Brown <broonie@kernel.org>; Tudor Ambarus
> <tudor.ambarus@microchip.com>; linux-mtd@lists.infradead.org; linux-
> spi@vger.kernel.org; marek.vasut@gmail.com; cyrille.pitchen@wedev4u.fr;
> computersforpeace@gmail.com; frieder.schrempf@exceet.de; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON flash
> 
> Hi Yogesh,
> 
> On Tue, 23 Oct 2018 09:39:25 +0000
> Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> wrote:
> 
> > Hi,
> >
> > Did we have have any comments or remarks about this patch-series,  if not
> please apply.
> 
> Sorry, but it was already too late for this release, and the merge window just
> started, so it will have to wait at least 2 more weeks.
Ok.

> 
> We've been lagging with SPI NOR patches for the last couple releases because I
> clearly don't have time to review those contributions, and it seems Marek does
> not have time either.
> 
> >
> > Both patches in the series been reviewed by Tudor.
> 
> Things are improving a bit thanks to Tudor's involvement in the review process,
> but I'd like to remember you that you, as a regular contributor to the spi-nor
> subsystem, can help us with that too. That is, help review patches coming from
> others instead of only focusing on your own contributions.
> 
Sure, I would start doing the review of other contributor patches.

--
Regards
Yogesh Gaur.

> Regards,
> 
> Boris
Yogesh Narayan Gaur Nov. 16, 2018, 6:54 a.m. UTC | #7 
Hi Boris,

Please apply this patch series [1] in the coming release.

--
Regards
Yogesh Gaur
[1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70384


> -----Original Message-----
> From: Yogesh Narayan Gaur
> Sent: Tuesday, October 23, 2018 3:31 PM
> To: 'Boris Brezillon' <boris.brezillon@bootlin.com>
> Cc: Mark Brown <broonie@kernel.org>; Tudor Ambarus
> <tudor.ambarus@microchip.com>; linux-mtd@lists.infradead.org; linux-
> spi@vger.kernel.org; marek.vasut@gmail.com; cyrille.pitchen@wedev4u.fr;
> computersforpeace@gmail.com; frieder.schrempf@exceet.de; linux-
> kernel@vger.kernel.org
> Subject: RE: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON flash
> 
> Hi Boris,
> 
> > -----Original Message-----
> > From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> > Sent: Tuesday, October 23, 2018 3:27 PM
> > To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
> > Cc: Mark Brown <broonie@kernel.org>; Tudor Ambarus
> > <tudor.ambarus@microchip.com>; linux-mtd@lists.infradead.org; linux-
> > spi@vger.kernel.org; marek.vasut@gmail.com;
> > cyrille.pitchen@wedev4u.fr; computersforpeace@gmail.com;
> > frieder.schrempf@exceet.de; linux- kernel@vger.kernel.org
> > Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON
> > flash
> >
> > Hi Yogesh,
> >
> > On Tue, 23 Oct 2018 09:39:25 +0000
> > Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> wrote:
> >
> > > Hi,
> > >
> > > Did we have have any comments or remarks about this patch-series,
> > > if not
> > please apply.
> >
> > Sorry, but it was already too late for this release, and the merge
> > window just started, so it will have to wait at least 2 more weeks.
> Ok.
> 
> >
> > We've been lagging with SPI NOR patches for the last couple releases
> > because I clearly don't have time to review those contributions, and
> > it seems Marek does not have time either.
> >
> > >
> > > Both patches in the series been reviewed by Tudor.
> >
> > Things are improving a bit thanks to Tudor's involvement in the review
> > process, but I'd like to remember you that you, as a regular
> > contributor to the spi-nor subsystem, can help us with that too. That
> > is, help review patches coming from others instead of only focusing on your
> own contributions.
> >
> Sure, I would start doing the review of other contributor patches.
> 
> --
> Regards
> Yogesh Gaur.
> 
> > Regards,
> >
> > Boris
Boris Brezillon Nov. 21, 2018, 2:39 p.m. UTC | #8 
On Fri, 2018-10-12 at 02:23:08 UTC, Yogesh Narayan Gaur wrote:
> Some MICRON related macros in spi-nor domain were ST.
> Rename entries related to STMicroelectronics under macro SNOR_MFR_ST.
> 
> Added entry of MFR Id for Micron flashes, 0x002C.
> 
> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>

Applied to http://git.infradead.org/linux-mtd.git spi-nor/next, thanks.

Boris
diff mbox series

Patch

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 9407ca5..b8b494f 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -284,6 +284,7 @@  static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
 	u8 cmd;
 
 	switch (JEDEC_MFR(info)) {
+	case SNOR_MFR_ST:
 	case SNOR_MFR_MICRON:
 		/* Some Micron need WREN command; all will accept it */
 		need_wren = true;
@@ -1388,7 +1389,7 @@  static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 	{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
 
-	/* Micron */
+	/* Micron <--> ST Micro */
 	{ "n25q016a",	 INFO(0x20bb15, 0, 64 * 1024,   32, SECT_4K | SPI_NOR_QUAD_READ) },
 	{ "n25q032",	 INFO(0x20ba16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) },
 	{ "n25q032a",	 INFO(0x20bb16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) },
@@ -3223,6 +3224,7 @@  static int spi_nor_init_params(struct spi_nor *nor,
 			params->quad_enable = macronix_quad_enable;
 			break;
 
+		case SNOR_MFR_ST:
 		case SNOR_MFR_MICRON:
 			break;
 
@@ -3671,8 +3673,9 @@  int spi_nor_scan(struct spi_nor *nor, const char *name,
 	mtd->_resume = spi_nor_resume;
 
 	/* NOR protection support for STmicro/Micron chips and similar */
-	if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
-			info->flags & SPI_NOR_HAS_LOCK) {
+	if (JEDEC_MFR(info) == SNOR_MFR_ST ||
+	    JEDEC_MFR(info) == SNOR_MFR_MICRON ||
+	    info->flags & SPI_NOR_HAS_LOCK) {
 		nor->flash_lock = stm_lock;
 		nor->flash_unlock = stm_unlock;
 		nor->flash_is_locked = stm_is_locked;
diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h
index 9b57a9b..cbf7716 100644
--- a/include/linux/mtd/cfi.h
+++ b/include/linux/mtd/cfi.h
@@ -377,6 +377,7 @@  struct cfi_fixup {
 #define CFI_MFR_SHARP		0x00B0
 #define CFI_MFR_SST		0x00BF
 #define CFI_MFR_ST		0x0020 /* STMicroelectronics */
+#define CFI_MFR_MICRON		0x002C /* Micron */
 #define CFI_MFR_TOSHIBA		0x0098
 #define CFI_MFR_WINBOND		0x00DA
 
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 7f0c730..8b1acf6 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -23,7 +23,8 @@ 
 #define SNOR_MFR_ATMEL		CFI_MFR_ATMEL
 #define SNOR_MFR_GIGADEVICE	0xc8
 #define SNOR_MFR_INTEL		CFI_MFR_INTEL
-#define SNOR_MFR_MICRON		CFI_MFR_ST /* ST Micro <--> Micron */
+#define SNOR_MFR_ST		CFI_MFR_ST	/* ST Micro */
+#define SNOR_MFR_MICRON		CFI_MFR_MICRON	/* Micron */
 #define SNOR_MFR_MACRONIX	CFI_MFR_MACRONIX
 #define SNOR_MFR_SPANSION	CFI_MFR_AMD
 #define SNOR_MFR_SST		CFI_MFR_SST