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Fri, 12 Oct 2018 02:23:13 +0000 Received: from VI1PR04MB1038.eurprd04.prod.outlook.com ([fe80::d887:3c96:479a:4123]) by VI1PR04MB1038.eurprd04.prod.outlook.com ([fe80::d887:3c96:479a:4123%3]) with mapi id 15.20.1207.024; Fri, 12 Oct 2018 02:23:13 +0000 From: Yogesh Narayan Gaur To: "linux-mtd@lists.infradead.org" , "linux-spi@vger.kernel.org" , "tudor.ambarus@microchip.com" CC: "marek.vasut@gmail.com" , "cyrille.pitchen@wedev4u.fr" , "boris.brezillon@bootlin.com" , "computersforpeace@gmail.com" , "frieder.schrempf@exceet.de" , "linux-kernel@vger.kernel.org" , Yogesh Narayan Gaur Subject: [PATCH v3 2/2] mtd: spi-nor: add entry for mt35xu512aba flash Thread-Topic: [PATCH v3 2/2] mtd: spi-nor: add entry for mt35xu512aba flash Thread-Index: AQHUYdKGKD+kbaBkdUSmApnPC/zheg== Date: Fri, 12 Oct 2018 02:23:13 +0000 Message-ID: <1539310881-17438-3-git-send-email-yogeshnarayan.gaur@nxp.com> References: <1539310881-17438-1-git-send-email-yogeshnarayan.gaur@nxp.com> In-Reply-To: <1539310881-17438-1-git-send-email-yogeshnarayan.gaur@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SG2PR06CA0225.apcprd06.prod.outlook.com (2603:1096:4:68::33) To VI1PR04MB1038.eurprd04.prod.outlook.com (2a01:111:e400:5092::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=yogeshnarayan.gaur@nxp.com; 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This flash is having uniform sector erase size of 128KB, have support of FSR(flag status register), flash size is 64MB and supports 4-byte commands. Signed-off-by: Yogesh Gaur Reviewed-by: Tudor Ambarus --- Changes for v3: - Modified flash node style as suggested by Tudor. Changes for v2: - Removed checkpatch warning, 80 character limit. drivers/mtd/spi-nor/spi-nor.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index b8b494f..0b8a6e0 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1405,6 +1405,12 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, + /* Micron */ + { + "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512, + SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES) + }, + /* PMC */ { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) }, { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },