From patchwork Wed Nov 7 14:43:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 10672489 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3E2EE14D6 for ; Wed, 7 Nov 2018 14:56:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2B7382BE06 for ; Wed, 7 Nov 2018 14:56:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1EB8E2BE02; Wed, 7 Nov 2018 14:56:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8F6C82BE02 for ; Wed, 7 Nov 2018 14:56:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731034AbeKHA0o (ORCPT ); Wed, 7 Nov 2018 19:26:44 -0500 Received: from mo4-p05-ob.smtp.rzone.de ([85.215.255.133]:26064 "EHLO mo4-p05-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387788AbeKHA0n (ORCPT ); Wed, 7 Nov 2018 19:26:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1541602559; s=strato-dkim-0002; d=as-electronics.de; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=eyAMa4jxAybAUfKZyOz03nHzABmuowAaRchxukYjamI=; b=geleidNxlCE/RxXa0rWxxL07OnHt3MIX4zBz5Lc3a7/QRTt8ZmiClyRCiXz8cxSqii p3MLOLthb/+2W9UqDtM5AmSDkzDORdhs/CnNoubmOk8m7eiO0sbCWisXuiZSOFXUfJao 3Ym0urUQMqFF43oh4S8BU9LpToi92vwCzMWq0qkAgZtZBf6IjD07eweYjg7x6uZG6vNP k/0+r7u/TJQaAe/xBghyEAp/kTrFsDkz9dWKfksRRmVa03GJFypqiXnFj1Tcz6Nt7y0y ug7jMYzNxgrKZtKEg9TQJu/dsrxxLmZ33EN1PCyUPWImGP6TW4oysQ9eJbNX3XIjmxfP SgTA== X-RZG-AUTH: ":LX8JdEmkW/4tAFwMkcNJIloh1hrA5u3owhPk7bdT5Fx22AatU+eLaHfutoZdl+X9BETxn4/4+IVqx7ZdE8mPU5nMS5P2QgHAetWm5FNngAjmE0pFNjw=" X-RZG-CLASS-ID: mo05 Received: from fs-work.fritz.box by smtp.strato.de (RZmta 44.3 AUTH) with ESMTPSA id j097e4uA7EiCUQm (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (curve secp521r1 with 521 ECDH bits, eq. 15360 bits RSA)) (Client did not present a certificate); Wed, 7 Nov 2018 15:44:12 +0100 (CET) From: Frieder Schrempf To: linux-mtd@lists.infradead.org, boris.brezillon@bootlin.com, linux-spi@vger.kernel.org Cc: dwmw2@infradead.org, computersforpeace@gmail.com, marek.vasut@gmail.com, richard@nod.at, miquel.raynal@bootlin.com, broonie@kernel.org, david.wolfe@nxp.com, fabio.estevam@nxp.com, prabhakar.kushwaha@nxp.com, yogeshnarayan.gaur@nxp.com, han.xu@nxp.com, shawnguo@kernel.org, Frieder Schrempf , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 03/10] dt-bindings: spi: Adjust the bindings for the FSL QSPI driver Date: Wed, 7 Nov 2018 15:43:20 +0100 Message-Id: <1541601809-16950-4-git-send-email-frieder.schrempf@kontron.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1541601809-16950-1-git-send-email-frieder.schrempf@kontron.de> References: <1541601809-16950-1-git-send-email-frieder.schrempf@kontron.de> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Frieder Schrempf Adjust the documentation of the new SPI memory interface based driver to reflect the new drivers settings. The "old" driver was using the "fsl,qspi-has-second-chip" property to select one of two dual chip setups (two chips on one bus or two chips on separate buses). And it used the order in which the subnodes are defined in the dt to select the CS, the chip is connected to. Both methods are wrong and in fact the "reg" property should be used to determine which bus and CS a chip is connected to. This also enables us to use different setups than just single chip, or symmetric dual chip. So the porting of the driver from the MTD to the SPI framework actually enforces the use of the "reg" properties and makes "fsl,qspi-has-second-chip" superfluous. As all boards that have "fsl,qspi-has-second-chip" set, also have correct "reg" properties, the removal of this property shouldn't lead to any incompatibilities. The only compatibility issues I can see are with imx6sx-sdb.dts and imx6sx-sdb-reva.dts, which have their reg properties set incorrectly (see explanation here: [2]), all other boards should stay compatible. Also the "big-endian" flag was removed, as this setting is now selected by the driver, depending on which SoC is in use. Signed-off-by: Frieder Schrempf --- .../devicetree/bindings/spi/spi-fsl-qspi.txt | 21 +++++++++----------- 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt index 483e9cf..6d7c9ec 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt @@ -3,9 +3,8 @@ Required properties: - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi", "fsl,imx7d-qspi", "fsl,imx6ul-qspi", - "fsl,ls1021a-qspi" + "fsl,ls1021a-qspi", "fsl,ls2080a-qspi" or - "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi", "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi" - reg : the first contains the register location and length, the second contains the memory mapping address and length @@ -14,15 +13,13 @@ Required properties: - clocks : The clocks needed by the QuadSPI controller - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi". -Optional properties: - - fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B. - Each bus can be connected with two NOR flashes. - Most of the time, each bus only has one NOR flash - connected, this is the default case. - But if there are two NOR flashes connected to the - bus, you should enable this property. - (Please check the board's schematic.) - - big-endian : That means the IP register is big endian +Required SPI slave node properties: + - reg: There are two buses (A and B) with two chip selects each. + This encodes to which bus and CS the flash is connected: + <0>: Bus A, CS 0 + <1>: Bus A, CS 1 + <2>: Bus B, CS 0 + <3>: Bus B, CS 1 Example: @@ -40,7 +37,7 @@ qspi0: quadspi@40044000 { }; }; -Example showing the usage of two SPI NOR devices: +Example showing the usage of two SPI NOR devices on bus A: &qspi2 { pinctrl-names = "default";