From patchwork Tue Feb 19 11:40:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yash Shah X-Patchwork-Id: 10819713 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5D3396C2 for ; Tue, 19 Feb 2019 11:40:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4A7362B63D for ; Tue, 19 Feb 2019 11:40:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3EB652B677; Tue, 19 Feb 2019 11:40:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DF3E62B6FA for ; Tue, 19 Feb 2019 11:40:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727927AbfBSLkv (ORCPT ); Tue, 19 Feb 2019 06:40:51 -0500 Received: from mail-pl1-f194.google.com ([209.85.214.194]:46094 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727048AbfBSLkv (ORCPT ); Tue, 19 Feb 2019 06:40:51 -0500 Received: by mail-pl1-f194.google.com with SMTP id o6so10319935pls.13 for ; Tue, 19 Feb 2019 03:40:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HIz4WqHdWYeQ3lkgJK9b2XM4IGZAxsw+zj/jLhdUw3c=; b=jPXPgTjADVt2+smuFo/EEaOowKhqwX/01aQQpu94dpBEHTRqdZHCopqJ48PyFWUn17 7KY8rIbKUV0L7zhDsDIbs7H3i7rOrmEXdlHQBwYSZ5KJXr3ivJiSOuLxL9VtQploH7vh 7Ens8nI7UIuMaOKegIVWFfkYf62F/5wwxmXF3z7TXW+7WXASELjtG+uSqVbhl8RRYdJe ZowRGNrjstb/mKNMQ7t+il98T+91tjjz/gi3hpA9M11smQuV0WF7E3T9I34qPlxpPCqK mM7OO602/MJCNBkpR1OxbraamnM5CfA4PnM8PXu+68VbiIlNQxOeZ3qoGSFz41kUvv8i nqKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HIz4WqHdWYeQ3lkgJK9b2XM4IGZAxsw+zj/jLhdUw3c=; b=YW8ha51iYyHQ2LnblX0F0gDOfCkk6OWWM/oIEUNj7FuoK5bHHrjD2hz9J5naXGdPDb xob8GwdQ30u8/6kVDMVSqwJu8cdUWRDwW4ek1TSBN2nJ8ZqVtx20Xu0Ebi2bYnQFkJVq A+fB9lEWtf4D/yGNTUPY8lw1XOX8IXTU9KFSh+JSzN+XeGalIv4TAVpCAOQUneZO4LVB uVHYyZPpVbwG325cR4Y5xkd7T1MX88lsq1Oiree+E1m6WaiwjWzwbCLCRlzD2tkzEnJw DJJIK3UPY4HfSij4J2wO6Tp4SuVzuzcfgEYo9DrltNnnX0PxASuxQEGiXX5h/wsPofbz MIkw== X-Gm-Message-State: AHQUAuaB0ib/yQGAllszm77zaarETVKCukWzieQ/CvLQmUtwsDzBl2IF 7pESNZUT6fan1v5PFyYHUbk5y7puzGk= X-Google-Smtp-Source: AHgI3Ia4opb4C4j1RKzH/PI1euLWE6o1bbHCPXTT8YroDhOvbZoZL+hUVjvkrJu+a5QTkLZ7sMeHrw== X-Received: by 2002:a17:902:a514:: with SMTP id s20mr20268782plq.242.1550576450476; Tue, 19 Feb 2019 03:40:50 -0800 (PST) Received: from buildserver-90.open-silicon.com ([114.143.65.226]) by smtp.googlemail.com with ESMTPSA id t3sm32250678pfa.50.2019.02.19.03.40.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Feb 2019 03:40:49 -0800 (PST) From: Yash Shah To: palmer@sifive.com, linux-spi@vger.kernel.org, linux-riscv@lists.infradead.org, broonie@kernel.org Cc: robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, sachin.ghadi@sifive.com, paul.walmsley@sifive.com, Yash Shah Subject: [PATCH 1/2] spi: sifive: Add DT documentation for SiFive SPI controller Date: Tue, 19 Feb 2019 17:10:06 +0530 Message-Id: <1550576407-17778-2-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1550576407-17778-1-git-send-email-yash.shah@sifive.com> References: <1550576407-17778-1-git-send-email-yash.shah@sifive.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP DT documentation for SPI controller added. Signed-off-by: Palmer Dabbelt Signed-off-by: Emil Renner Berthing Signed-off-by: Yash Shah --- .../devicetree/bindings/spi/spi-sifive.txt | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-sifive.txt diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.txt b/Documentation/devicetree/bindings/spi/spi-sifive.txt new file mode 100644 index 0000000..3f5c6e4 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-sifive.txt @@ -0,0 +1,37 @@ +SiFive SPI controller Device Tree Bindings +------------------------------------------ + +Required properties: +- compatible : Should be "sifive,-spi" and "sifive,spi". + Supported compatible strings are: + "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated + onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive + SPI v0 IP block with no chip integration tweaks. + Please refer to sifive-blocks-ip-versioning.txt for details +- reg : Physical base address and size of SPI registers map + A second (optional) range can indicate memory mapped flash +- interrupts : Must contain one entry +- interrupt-parent : Must be core interrupt controller +- clocks : Must reference the frequency given to the controller +- #address-cells : Must be '1', indicating which CS to use +- #size-cells : Must be '0' + +Optional properties: +- sifive,fifo-depth : Depth of hardware queues; defaults to 8 +- sifive,max-bits-per-word : Maximum bits per word; defaults to 8 + +SPI RTL that corresponds to the IP block version numbers can be found here: +https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi + +Example: + spi: spi@10040000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent = <&plic>; + interrupts = <51>; + clocks = <&tlclk>; + #address-cells = <1>; + #size-cells = <0>; + sifive,fifo-depth = <8>; + sifive,max-bits-per-word = <8>; + };