From patchwork Wed Mar 27 05:56:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872623 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 510531575 for ; Wed, 27 Mar 2019 05:58:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3B1B028CD8 for ; Wed, 27 Mar 2019 05:58:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2EEC428CDA; Wed, 27 Mar 2019 05:58:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C514428CD7 for ; Wed, 27 Mar 2019 05:58:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733302AbfC0F5s (ORCPT ); Wed, 27 Mar 2019 01:57:48 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:6275 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725795AbfC0F5q (ORCPT ); Wed, 27 Mar 2019 01:57:46 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 22:57:43 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:45 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 26 Mar 2019 22:57:45 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:44 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:44 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:44 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 24/26] spi: tegra114: de-assert CS before SPI mode is reset to its default Date: Tue, 26 Mar 2019 22:56:45 -0700 Message-ID: <1553666207-11414-24-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666263; bh=qqcxJt6Vkn8IPNbfhZkyYZ2kfpA+TQeqAqxGiomjZbY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=j/YsHbxJBF8Tt7C+TuyXooW6iNYA4KM+B6lpkBm9ej7etjTtdle8lJ3RRj5t4lE+T NGD2K3aNngR5QNoHMPZq2qbh/2pYH9sYSch7neZq6RrI7vj2BnOe8PG1JV6Iiu6xLl BsMc4rz7Tot9hH4recMkPu7e7ODZ9DiEHFdxSrQrvH+8iVbZrJEwoxJTylu6Z8EC+v XHppunBEnmaSr1DzwoUMrHzcuDn8Do83W7JBojOwTyTboNzAhF/xVv01uzVuD7CBbv xs7Ixeome1T9ahFqvXG/QyNodoLH/+umw00dvbd7nAnibwHcgV41uqBDYzP/67ZvoG vB2tVec/+Bqtw== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP With SW CS, during transfer completion CS is de-asserted by writing the default command1 register value to SPI_COMMAND1 register. With this both mode and CS state are set at the same time and if current transfer mode is different to default SPI mode and if mode change happens prior to CS de-assert, clock polarity can change while CS is active before transfer finishes. This causes Slave to see spurious clock edges resulting in data mismatch. This patch fixes this by de-asserting CS before writing SPI_COMMAND1 to its default value so through out the transfer it will be in same SPI mode. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 9b216e9d6079..e1669ab3b0fe 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -1147,6 +1147,12 @@ static int tegra_spi_transfer_one_message(struct spi_master *master, if (ret < 0 || skip) { if (cstate->cs_gpio_valid) gpio_set_value(spi->cs_gpio, cs_val); + if (cs_val && !tspi->use_hw_based_cs) + tspi->command1_reg |= SPI_CS_SW_VAL; + else + tspi->command1_reg &= ~SPI_CS_SW_VAL; + tegra_spi_writel(tspi, tspi->command1_reg, + SPI_COMMAND1); tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); tegra_spi_transfer_delay(xfer->delay_usecs); @@ -1158,6 +1164,12 @@ static int tegra_spi_transfer_one_message(struct spi_master *master, else { if (cstate->cs_gpio_valid) gpio_set_value(spi->cs_gpio, cs_val); + if (cs_val && !tspi->use_hw_based_cs) + tspi->command1_reg |= SPI_CS_SW_VAL; + else + tspi->command1_reg &= ~SPI_CS_SW_VAL; + tegra_spi_writel(tspi, tspi->command1_reg, + SPI_COMMAND1); tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); tegra_spi_transfer_delay(xfer->delay_usecs); @@ -1165,6 +1177,12 @@ static int tegra_spi_transfer_one_message(struct spi_master *master, } else if (xfer->cs_change) { if (cstate->cs_gpio_valid) gpio_set_value(spi->cs_gpio, cs_val); + if (cs_val && !tspi->use_hw_based_cs) + tspi->command1_reg |= SPI_CS_SW_VAL; + else + tspi->command1_reg &= ~SPI_CS_SW_VAL; + tegra_spi_writel(tspi, tspi->command1_reg, + SPI_COMMAND1); tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); tegra_spi_transfer_delay(xfer->delay_usecs);