From patchwork Fri Apr 5 00:14:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10886707 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C92331708 for ; Fri, 5 Apr 2019 00:15:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B6E2628958 for ; Fri, 5 Apr 2019 00:15:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AA33D28AEF; Fri, 5 Apr 2019 00:15:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 36B6828958 for ; Fri, 5 Apr 2019 00:15:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730668AbfDEAPb (ORCPT ); Thu, 4 Apr 2019 20:15:31 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:11316 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730648AbfDEAOc (ORCPT ); Thu, 4 Apr 2019 20:14:32 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 04 Apr 2019 17:14:29 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 04 Apr 2019 17:14:31 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 04 Apr 2019 17:14:31 -0700 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 5 Apr 2019 00:14:31 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 5 Apr 2019 00:14:31 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.103.48]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 04 Apr 2019 17:14:30 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V2 12/20] spi: tegra114: add support for LSBYTE_FIRST Date: Thu, 4 Apr 2019 17:14:11 -0700 Message-ID: <1554423259-26056-12-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554423259-26056-1-git-send-email-skomatineni@nvidia.com> References: <1554423259-26056-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1554423269; bh=2E8oRAtPhJTeCHSxIlRHTV5Bt06fc2aYd4dB6HrI5sU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=N9Gcv/VTVJ5o9J38waU6cG59gTFfNZcCL2N1zvlvMUP6G+t9Nj/EU/Tu5FI2H5yBl G5ZLV/HeCjUgdWtsuzZLwE10GWOmlIEfOYtlqovqm9mhjz05KcDqQ6vnMMOU92d0uk mpsUUnk/9N67omfzTY7wr8buidJkLwgMKDKNHhdN+NCFx9cU6ukwapEMyKUnXk2LAL 7if7C+LG5dhXUMuta2CXHKQApvvoskabiiYr2TcO8WYNdXV8+FAhMC3QBuq4DeNt8t IQFfeNdBekHHteBArAxxdeV8ZYUUiXwpIyvGpG1RkOfEZka+nvwyOZaIojpFM9xR1T ilbc3LHeCTvtg== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some SPI devices expects SPI transfers to be in Least significant byte first order and some devices expect Most significant byte first order. This patch adds SPI_LSBYTE_FIRST to the supported SPI mode list and also configures Tegra SPI controller accordingly. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 212bb90aa0cb..d3b95bba2361 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -755,6 +755,11 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, else command1 &= ~SPI_LSBIT_FE; + if (spi->mode & SPI_LSBYTE_FIRST) + command1 |= SPI_LSBYTE_FE; + else + command1 &= ~SPI_LSBYTE_FE; + if (spi->mode & SPI_3WIRE) command1 |= SPI_BIDIROE; else @@ -1164,7 +1169,8 @@ static int tegra_spi_probe(struct platform_device *pdev) /* the spi->mode bits understood by this driver: */ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST | - SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE; + SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE | + SPI_LSBYTE_FIRST; master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); master->setup = tegra_spi_setup; master->transfer_one_message = tegra_spi_transfer_one_message;