From patchwork Tue May 14 05:03:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10942025 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 325D46C5 for ; Tue, 14 May 2019 05:04:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2318A285CD for ; Tue, 14 May 2019 05:04:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 15492285E0; Tue, 14 May 2019 05:04:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A37B9285CD for ; Tue, 14 May 2019 05:04:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726753AbfENFED (ORCPT ); Tue, 14 May 2019 01:04:03 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:17390 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726060AbfENFED (ORCPT ); Tue, 14 May 2019 01:04:03 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 13 May 2019 22:03:22 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 13 May 2019 22:04:01 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 13 May 2019 22:04:01 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 14 May 2019 05:04:01 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 14 May 2019 05:04:01 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 14 May 2019 05:04:01 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.159]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 13 May 2019 22:04:00 -0700 From: Sowjanya Komatineni To: , , , CC: , , , Sowjanya Komatineni Subject: [PATCH V5 2/4] spi: tegra114: add support for hw based cs Date: Mon, 13 May 2019 22:03:53 -0700 Message-ID: <1557810235-16401-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557810235-16401-1-git-send-email-skomatineni@nvidia.com> References: <1557810235-16401-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1557810202; bh=k2pwjMQe73pMINbpya/u7vDdSHArgZLiAfPjTQcuzGE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=OoU5zhbRrag6mliWTAA+1FY1XLvyQ48V+ccmLNzBenOel3OFyCsEQgT0YEIMJI1Id Cvq5mfAW/5Ax1HhlCcEhn6H06v041OOUotYaKrEYSUSTQ55v6BvqDYwVyDJKovh5qE KSPybjZXkl7K9oRo37MxiGpdVfwyTb2IxwaFta9CXE+ud8ya9wUcoEdT259hMyqxhJ KNWw5qxWLZEeuyqhU/Dn6jdXLFCp3B+lVRkx0Csjteg3vAoZLElTVmACJnSJvoyD1R X9Fwgofs6Gd1Ft/H9UA3n3Igu8eWc0cVJ7IZ7IMuoXBLjftM+3BOIKU0YhEFXoIXvw N9umHrbpBv7wg== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra SPI controller supports both HW and SW based CS control for SPI transfers. This patch adds support for HW based CS control where CS is driven to active state during the transfer and is driven inactive at the end of the transfer directly by the HW. This patch enables the use of HW based CS only for single transfers without cs_change request. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 39 +++++++++++++++++++++++++++------------ 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index f47417dd9edb..0cb0932d32fd 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -193,6 +193,7 @@ struct tegra_spi_data { unsigned dma_buf_size; unsigned max_buf_size; bool is_curr_dma_xfer; + bool use_hw_based_cs; struct completion rx_dma_complete; struct completion tx_dma_complete; @@ -723,7 +724,9 @@ static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi, } static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, - struct spi_transfer *t, bool is_first_of_msg) + struct spi_transfer *t, + bool is_first_of_msg, + bool is_single_xfer) { struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); u32 speed = t->speed_hz; @@ -780,11 +783,17 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, if (spi->cs_gpiod) gpiod_set_value(spi->cs_gpiod, 1); - command1 |= SPI_CS_SW_HW; - if (spi->mode & SPI_CS_HIGH) - command1 |= SPI_CS_SW_VAL; - else - command1 &= ~SPI_CS_SW_VAL; + if (is_single_xfer && !(t->cs_change)) { + tspi->use_hw_based_cs = true; + command1 &= ~(SPI_CS_SW_HW | SPI_CS_SW_VAL); + } else { + tspi->use_hw_based_cs = false; + command1 |= SPI_CS_SW_HW; + if (spi->mode & SPI_CS_HIGH) + command1 |= SPI_CS_SW_VAL; + else + command1 &= ~SPI_CS_SW_VAL; + } tegra_spi_writel(tspi, 0, SPI_COMMAND2); } else { @@ -905,11 +914,14 @@ static void tegra_spi_transfer_end(struct spi_device *spi) if (spi->cs_gpiod) gpiod_set_value(spi->cs_gpiod, 0); - if (cs_val) - tspi->command1_reg |= SPI_CS_SW_VAL; - else - tspi->command1_reg &= ~SPI_CS_SW_VAL; - tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1); + if (!tspi->use_hw_based_cs) { + if (cs_val) + tspi->command1_reg |= SPI_CS_SW_VAL; + else + tspi->command1_reg &= ~SPI_CS_SW_VAL; + tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1); + } + tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); } @@ -936,16 +948,19 @@ static int tegra_spi_transfer_one_message(struct spi_master *master, struct spi_device *spi = msg->spi; int ret; bool skip = false; + int single_xfer; msg->status = 0; msg->actual_length = 0; + single_xfer = list_is_singular(&msg->transfers); list_for_each_entry(xfer, &msg->transfers, transfer_list) { u32 cmd1; reinit_completion(&tspi->xfer_completion); - cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg); + cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg, + single_xfer); if (!xfer->len) { ret = 0;