| Message ID | 1570178133-21532-8-git-send-email-fabrizio.castro@bp.renesas.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add RZ/G2N MSIOF/RWDT/PCIEC support | expand |
On Fri, Oct 4, 2019 at 10:36 AM Fabrizio Castro <fabrizio.castro@bp.renesas.com> wrote: > The plan for the HiHope RZ/G2N board is to enable pciec0 by default, > and use pciec1 physical interface for SATA (as SATA and PCIE1 share > the same physical interface), therefore move pciec1 enabling away > from hihope-rzg2-ex. > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.5. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi index ae1ef2d..63e407a 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi @@ -85,10 +85,6 @@ status = "okay"; }; -&pciec1 { - status = "okay"; -}; - &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts index 6e33a3b..c754fca 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts +++ b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts @@ -13,3 +13,7 @@ compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m", "renesas,r8a774a1"; }; + +&pciec1 { + status = "okay"; +};
The plan for the HiHope RZ/G2N board is to enable pciec0 by default, and use pciec1 physical interface for SATA (as SATA and PCIE1 share the same physical interface), therefore move pciec1 enabling away from hihope-rzg2-ex. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> --- arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi | 4 ---- arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts | 4 ++++ 2 files changed, 4 insertions(+), 4 deletions(-)