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[1/6] dt-bindings: spi: Unify SPI DesignWare DT documents

Message ID 1575907443-26377-2-git-send-email-wan.ahmad.zainie.wan.mohamad@intel.com (mailing list archive)
State New, archived
Headers show
Series spi: dw: Add support for DesignWare DWC_ssi | expand

Commit Message

Wan Ahmad Zainie Dec. 9, 2019, 4:03 p.m. UTC 
From: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>

This patch will merge the content of the file spi-dw.txt into the file
snps,dw-apb-ssi.txt.

Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
---
 .../devicetree/bindings/spi/snps,dw-apb-ssi.txt    | 23 ++++++++++++++++------
 1 file changed, 17 insertions(+), 6 deletions(-)
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Patch

diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
index 3ed08ee9feba..59904bdbef66 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
@@ -1,13 +1,21 @@ 
 Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
 
 Required properties:
-- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
-  "jaguar2", or "amazon,alpine-dw-apb-ssi"
+
+- compatible : should be one of the following:
+  - "snps,dw-apb-ssi"
+  - "mscc,<soc>-spi", where soc is "ocelot" or "jaguar2"
+  - "amazon,alpine-dw-apb-ssi"
+
 - reg : The register base for the controller. For "mscc,<soc>-spi", a second
   register set is required (named ICPU_CFG:SPI_MST)
+
 - interrupts : One interrupt, used by the controller.
-- #address-cells : <1>, as required by generic SPI binding.
-- #size-cells : <0>, also as required by generic SPI binding.
+
+- #address-cells : <1>, as required by generic SPI binding. See spi-bus.txt.
+
+- #size-cells : <0>, also as required by generic SPI binding. See spi-bus.txt.
+
 - clocks : phandles for the clocks, see the description of clock-names below.
    The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock
    is optional. If a single clock is specified but no clock-name, it is the
@@ -18,12 +26,15 @@  Optional properties:
     "ssi_clk", for the core clock used to generate the external SPI clock.
     "pclk", the interface clock, required for register access. If a clock domain
      used to enable this clock then it should be named "pclk_clkdomain".
+
 - cs-gpios : Specifies the gpio pins to be used for chipselects.
+
 - num-cs : The number of chipselects. If omitted, this will default to 4.
+
 - reg-io-width : The I/O register width (in bytes) implemented by this
-  device.  Supported values are 2 or 4 (the default).
+  device. Supported values are 2 or 4 (the default).
 
-Child nodes as per the generic SPI binding.
+Child nodes as per the generic SPI binding. See spi-bus.txt.
 
 Example: