| Message ID | 1588919619-21355-5-git-send-email-akashast@codeaurora.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add interconnect support to QSPI and QUP drivers | expand |
On Fri, May 08, 2020 at 12:03:36PM +0530, Akash Asthana wrote: > Get the interconnect paths for SPI based Serial Engine device > and vote according to the current bus speed of the driver. Acked-by: Mark Brown <broonie@kernel.org>
On Fri, May 08, 2020 at 12:03:36PM +0530, Akash Asthana wrote: > Get the interconnect paths for SPI based Serial Engine device > and vote according to the current bus speed of the driver. > > Signed-off-by: Akash Asthana <akashast@codeaurora.org> > --- > Changes in V2: > - As per Bjorn's comment, removed se == NULL check from geni_spi_icc_get > - As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure > - As per Bjorn's comment, introduced and using devm_of_icc_get API for getting > path handle > - As per Matthias comment, added error handling for icc_set_bw call > > Changes in V3: > - As per Matthias's comment, use helper ICC function from geni-se driver. > > Changes in V4: > - Move peak_bw guess as twice of avg_bw if nothing mentioned explicitly > to ICC core. > > Changes in V5: > - Use icc_enable/disable in power on/off call. > - Save some non-zero avg/peak value to ICC core by calling geni_icc_set_bw > from probe so that when resume/icc_enable is called NOC are running at > some non-zero value. No need to call icc_disable after BW vote because > device will resume and suspend before probe return and will leave ICC in > disabled state. > > drivers/spi/spi-geni-qcom.c | 32 +++++++++++++++++++++++++++++++- > 1 file changed, 31 insertions(+), 1 deletion(-) > > diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c > index c397242..5dfa1fb 100644 > --- a/drivers/spi/spi-geni-qcom.c > +++ b/drivers/spi/spi-geni-qcom.c > @@ -234,6 +234,13 @@ static int setup_fifo_params(struct spi_device *spi_slv, > return ret; > } > > + /* Set BW quota for CPU as driver supports FIFO mode only. */ > + geni_icc_bw_init(&se->icc_paths[CPU_TO_GENI], > + Bps_to_icc(mas->cur_speed_hz), 0); > + ret = geni_icc_set_bw(se); > + if (ret) > + return ret; > + > clk_sel = idx & CLK_SEL_MSK; > m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN; > spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); > @@ -578,6 +585,19 @@ static int spi_geni_probe(struct platform_device *pdev) > spin_lock_init(&mas->lock); > pm_runtime_enable(dev); > > + ret = geni_icc_get(&mas->se, NULL); > + if (ret) > + goto spi_geni_probe_runtime_disable; > + /* Set the bus quota to a reasonable value for register access */ > + geni_icc_bw_init(&mas->se.icc_paths[GENI_TO_CORE], > + Bps_to_icc(CORE_2X_50_MHZ), 0); > + geni_icc_bw_init(&mas->se.icc_paths[CPU_TO_GENI], GENI_DEFAULT_BW, 0); > + > + /* Set BW for register access */ This comment doesn't add any value. Register access is mentioned a few lines above and from the function name it's evident that it sets the ICC bandwidth. > + ret = geni_icc_set_bw(&mas->se); > + if (ret) > + goto spi_geni_probe_runtime_disable; > + > ret = spi_geni_init(mas); > if (ret) > goto spi_geni_probe_runtime_disable; > @@ -616,14 +636,24 @@ static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) > { > struct spi_master *spi = dev_get_drvdata(dev); > struct spi_geni_master *mas = spi_master_get_devdata(spi); > + int ret; > + > + ret = geni_se_resources_off(&mas->se); > + if (ret) > + return ret; > > - return geni_se_resources_off(&mas->se); > + return geni_icc_disable(&mas->se); > } > > static int __maybe_unused spi_geni_runtime_resume(struct device *dev) > { > struct spi_master *spi = dev_get_drvdata(dev); > struct spi_geni_master *mas = spi_master_get_devdata(spi); > + int ret; > + > + ret = geni_icc_enable(&mas->se); > + if (ret) > + return ret; > > return geni_se_resources_on(&mas->se); > } Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Hi Matthias, .... ; >> >> + ret = geni_icc_get(&mas->se, NULL); >> + if (ret) >> + goto spi_geni_probe_runtime_disable; >> + /* Set the bus quota to a reasonable value for register access */ >> + geni_icc_bw_init(&mas->se.icc_paths[GENI_TO_CORE], >> + Bps_to_icc(CORE_2X_50_MHZ), 0); >> + geni_icc_bw_init(&mas->se.icc_paths[CPU_TO_GENI], GENI_DEFAULT_BW, 0); >> + >> + /* Set BW for register access */ > This comment doesn't add any value. Register access is mentioned a few lines > above and from the function name it's evident that it sets the ICC bandwidth. ok > >> + ret = geni_icc_set_bw(&mas->se); >> >> + return ret; >> >> return geni_se_resources_on(&mas->se); >> } > Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c index c397242..5dfa1fb 100644 --- a/drivers/spi/spi-geni-qcom.c +++ b/drivers/spi/spi-geni-qcom.c @@ -234,6 +234,13 @@ static int setup_fifo_params(struct spi_device *spi_slv, return ret; } + /* Set BW quota for CPU as driver supports FIFO mode only. */ + geni_icc_bw_init(&se->icc_paths[CPU_TO_GENI], + Bps_to_icc(mas->cur_speed_hz), 0); + ret = geni_icc_set_bw(se); + if (ret) + return ret; + clk_sel = idx & CLK_SEL_MSK; m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN; spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); @@ -578,6 +585,19 @@ static int spi_geni_probe(struct platform_device *pdev) spin_lock_init(&mas->lock); pm_runtime_enable(dev); + ret = geni_icc_get(&mas->se, NULL); + if (ret) + goto spi_geni_probe_runtime_disable; + /* Set the bus quota to a reasonable value for register access */ + geni_icc_bw_init(&mas->se.icc_paths[GENI_TO_CORE], + Bps_to_icc(CORE_2X_50_MHZ), 0); + geni_icc_bw_init(&mas->se.icc_paths[CPU_TO_GENI], GENI_DEFAULT_BW, 0); + + /* Set BW for register access */ + ret = geni_icc_set_bw(&mas->se); + if (ret) + goto spi_geni_probe_runtime_disable; + ret = spi_geni_init(mas); if (ret) goto spi_geni_probe_runtime_disable; @@ -616,14 +636,24 @@ static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) { struct spi_master *spi = dev_get_drvdata(dev); struct spi_geni_master *mas = spi_master_get_devdata(spi); + int ret; + + ret = geni_se_resources_off(&mas->se); + if (ret) + return ret; - return geni_se_resources_off(&mas->se); + return geni_icc_disable(&mas->se); } static int __maybe_unused spi_geni_runtime_resume(struct device *dev) { struct spi_master *spi = dev_get_drvdata(dev); struct spi_geni_master *mas = spi_master_get_devdata(spi); + int ret; + + ret = geni_icc_enable(&mas->se); + if (ret) + return ret; return geni_se_resources_on(&mas->se); }
Get the interconnect paths for SPI based Serial Engine device and vote according to the current bus speed of the driver. Signed-off-by: Akash Asthana <akashast@codeaurora.org> --- Changes in V2: - As per Bjorn's comment, removed se == NULL check from geni_spi_icc_get - As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure - As per Bjorn's comment, introduced and using devm_of_icc_get API for getting path handle - As per Matthias comment, added error handling for icc_set_bw call Changes in V3: - As per Matthias's comment, use helper ICC function from geni-se driver. Changes in V4: - Move peak_bw guess as twice of avg_bw if nothing mentioned explicitly to ICC core. Changes in V5: - Use icc_enable/disable in power on/off call. - Save some non-zero avg/peak value to ICC core by calling geni_icc_set_bw from probe so that when resume/icc_enable is called NOC are running at some non-zero value. No need to call icc_disable after BW vote because device will resume and suspend before probe return and will leave ICC in disabled state. drivers/spi/spi-geni-qcom.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-)