| Message ID | 1643970576-31503-6-git-send-email-kyarlagadda@nvidia.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Tegra QUAD SPI combined sequence mode | expand |
On Fri, Feb 04, 2022 at 03:59:35PM +0530, Krishna Yarlagadda wrote: > + nvidia,cmb-xfer: > + description: > + Enable combined sequence transfers for read and program sequence > + if supported by hardware. Tegra194 and later chips support this > + feature. Default is non combined sequence. SPI message should > + contain CMD-ADDR-DATA transfers to combine and send to hardware. > + type: boolean Why is this a DT property - why would systems not wish to use this feature if it is available?
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml index 6efea89..3767059 100644 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml @@ -46,6 +46,14 @@ properties: - const: rx - const: tx + nvidia,cmb-xfer: + description: + Enable combined sequence transfers for read and program sequence + if supported by hardware. Tegra194 and later chips support this + feature. Default is non combined sequence. SPI message should + contain CMD-ADDR-DATA transfers to combine and send to hardware. + type: boolean + patternProperties: "@[0-9a-f]+": type: object
Tegra194 and later chips support combined sequence mode which result in less interrupts and better perf. This flag helps enable it. Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> --- Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml | 8 ++++++++ 1 file changed, 8 insertions(+)