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Fri, 4 Feb 2022 02:30:12 -0800 From: Krishna Yarlagadda To: , , , , CC: , , , , , , Krishna Yarlagadda Subject: [PATCH 5/6] dt-bindings: spi: Tegra QUAD SPI combined sequence Date: Fri, 4 Feb 2022 15:59:35 +0530 Message-ID: <1643970576-31503-6-git-send-email-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1643970576-31503-1-git-send-email-kyarlagadda@nvidia.com> References: <1643970576-31503-1-git-send-email-kyarlagadda@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3fe058a0-2d94-4850-7627-08d9e7c9568d X-MS-TrafficTypeDiagnostic: BN6PR12MB1252:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3968; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6VuShDXyRF6e4xXW3/QbmBgSKqhlzZvyeQs+5n5n4R4D3rGkZWpVkyEzkA6d9lWEFLFWnT6P32B7NOn28iBqEOLrAgGU7WD9XCIl/6Dlxb7ZwhBF4Ah4E8kvOQ2eY/siVVJ4D0yAB5WVwpnOSu/P2AONckQiS2dYmVauIRMB/jQnODG12iVaadKLU8t798y4skVMKIrQ0Ad+71lnU4ONgwYXblvDTwaaf4z8omYWY2a7qpkbPFZQNoem6EGZBli8avD6Y6n8hbaVTv/7rnbGhpaxsMamOjDdYR9JX3mi6wSY/76XXL4jmBIRinuqar5HK8G/pw1a2hqXgtcu7lOLuOjzX7JcpbX83KQk5VsrpgCR9pSf2JHctaVqpSt6zan0Rj0w/yJ8Qnxx4PNSn/Zz6xpBNXAmhAtVES8Y9hg6F8pdv0q/XPbaxi2zahWXiHWmIM07c+3hSqgHjCVPQeMs3ecUJSYrQEchtca86oVUevX4Yal/HGOxJIMReskz0fS1eLX5KIYYLLLRo+Kt3eV28aN37SoV9CF4AsSuKBn5CNZeD+ioPWCC3rn/t/g0AjW+bF0AU0JkaRwL+hSy+Y7cObmVPPxGDVHkcqkf42FcJZWllRWKSEecFCoGcWJJB88zQHmkvOxgNP6Mhx1T/al1K8qH8Pe/+rtXsRCZnjRhDZNMllCDZfj1OobjHide8qJSAW8Ss2MAfANTR8sOkVRVYQ== X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(86362001)(82310400004)(40460700003)(356005)(70206006)(8936002)(8676002)(4326008)(70586007)(316002)(110136005)(54906003)(81166007)(5660300002)(7696005)(107886003)(36860700001)(83380400001)(47076005)(508600001)(2616005)(6666004)(336012)(186003)(26005)(426003)(36756003)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2022 10:30:17.4940 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3fe058a0-2d94-4850-7627-08d9e7c9568d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1252 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Tegra194 and later chips support combined sequence mode which result in less interrupts and better perf. This flag helps enable it. Signed-off-by: Krishna Yarlagadda --- Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml index 6efea89..3767059 100644 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml @@ -46,6 +46,14 @@ properties: - const: rx - const: tx + nvidia,cmb-xfer: + description: + Enable combined sequence transfers for read and program sequence + if supported by hardware. Tegra194 and later chips support this + feature. Default is non combined sequence. SPI message should + contain CMD-ADDR-DATA transfers to combine and send to hardware. + type: boolean + patternProperties: "@[0-9a-f]+": type: object