diff mbox series

[09/11] mtd: spi-nor: macronix: add mx25uw51345g OPI mode support

Message ID 1657012303-6464-9-git-send-email-haibo.chen@nxp.com (mailing list archive)
State New, archived
Headers show
Series [01/11] spi: spi-nxp-fspi: enable runtime pm for fspi | expand

Commit Message

Bough Chen July 5, 2022, 9:11 a.m. UTC 
From: Haibo Chen <haibo.chen@nxp.com>

mx25uw51345g has a special OPI DTR read command id, so add this
special fixup.
For RDID under OPI DTR mode, the dummy need to enlarge to 20 cycles,
otherwise can't get correct ID value.

Acked-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 drivers/mtd/spi-nor/macronix.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

Comments

Michael Walle July 18, 2022, 6:57 a.m. UTC | #1 
Am 2022-07-05 11:11, schrieb haibo.chen@nxp.com:
> From: Haibo Chen <haibo.chen@nxp.com>
> 
> mx25uw51345g has a special OPI DTR read command id, so add this
> special fixup.
> For RDID under OPI DTR mode, the dummy need to enlarge to 20 cycles,
> otherwise can't get correct ID value.

Could you please dump the SFDP data of this flash, see [1]. I wonder
if this command isn't described in the SFDP.

-michael

[1] 
https://lore.kernel.org/linux-mtd/4304e19f3399a0a6e856119d01ccabe0@walle.cc/
diff mbox series

Patch

diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index b4f4d8185cce..99140fc9305b 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -13,6 +13,7 @@ 
 #define SPINOR_REG_MXIC_CR2_MODE	0x00000000	/* For setting octal DTR mode */
 #define SPINOR_REG_MXIC_OPI_DTR_EN	0x2		/* Enable Octal DTR */
 #define SPINOR_REG_MXIC_SPI_EN		0x0		/* Enable SPI */
+#define SPINOR_OP_OPI_DTR_RD		0xEE		/* OPI DTR first read opcode */
 
 static int
 mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
@@ -117,6 +118,19 @@  static struct spi_nor_fixups octaflash_fixups = {
 	.default_init = octaflash_default_init,
 };
 
+static void mx25uw51345g_post_sfdp_fixup(struct spi_nor *nor)
+{
+	nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
+	spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR],
+				  0, 20, SPINOR_OP_OPI_DTR_RD,
+				  SNOR_PROTO_8_8_8_DTR);
+}
+
+static struct spi_nor_fixups mx25uw51345g_fixups = {
+	.default_init = octaflash_default_init,
+	.post_sfdp = mx25uw51345g_post_sfdp_fixup,
+};
+
 static const struct flash_info macronix_nor_parts[] = {
 	/* Macronix */
 	{ "mx25l512e",   INFO(0xc22010, 0, 64 * 1024,   1)
@@ -264,7 +278,7 @@  static const struct flash_info macronix_nor_parts[] = {
 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
 			      SPI_NOR_OCTAL_DTR_PP)
 		FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
-		.fixups = &octaflash_fixups },
+		.fixups = &mx25uw51345g_fixups },
 	{ "mx25um25645g", INFO(0xc28039, 0, 8 * 1024, 4096)
 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
 			      SPI_NOR_OCTAL_DTR_PP)