From patchwork Wed Feb 17 18:19:00 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ernst Schwab X-Patchwork-Id: 80002 Received: from lists.sourceforge.net (lists.sourceforge.net [216.34.181.88]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o1HIJ9Ep026791 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 17 Feb 2010 18:19:45 GMT Received: from localhost ([127.0.0.1] helo=sfs-ml-3.v29.ch3.sourceforge.com) by sfs-ml-3.v29.ch3.sourceforge.com with esmtp (Exim 4.69) (envelope-from ) id 1NhoUP-0003ij-By; Wed, 17 Feb 2010 18:19:09 +0000 Received: from sfi-mx-1.v28.ch3.sourceforge.com ([172.29.28.121] helo=mx.sourceforge.net) by sfs-ml-3.v29.ch3.sourceforge.com with esmtp (Exim 4.69) (envelope-from ) id 1NhoUN-0003hM-Kp for spi-devel-general@lists.sourceforge.net; Wed, 17 Feb 2010 18:19:07 +0000 X-ACL-Warn: Received: from moutng.kundenserver.de ([212.227.126.186]) by sfi-mx-1.v28.ch3.sourceforge.com with esmtp (Exim 4.69) id 1NhoUL-0003Gh-4e; Wed, 17 Feb 2010 18:19:07 +0000 Received: from ip065 (koln-5d811195.pool.mediaWays.net [93.129.17.149]) by mrelayeu.kundenserver.de (node=mreu1) with ESMTP (Nemesis) id 0MJYNz-1NgRZq0TZT-003GtQ; Wed, 17 Feb 2010 19:18:58 +0100 Date: Wed, 17 Feb 2010 19:19:00 +0100 From: Ernst Schwab To: Grant Likely , Kumar Gala , David Brownell Message-Id: <20100217191900.a57d0a60.eschwab@online.de> In-Reply-To: <20100217191513.52392dd6.eschwab@online.de> References: <20100217191513.52392dd6.eschwab@online.de> X-Mailer: Sylpheed 3.0.0beta8 (GTK+ 2.10.14; i686-pc-mingw32) Mime-Version: 1.0 X-Provags-ID: V01U2FsdGVkX19BAPr92LWhkNn6qPCKlqI9gycQgzgW07wNA1m QBwHPT8QeI+JuMVfBMTxuTK35Hn6sbJuHrTrBYfBCeEOXlnEm8 NH/Nynec6Cl4F1SRADGnDDMp4BCfRiP X-Spam-Score: 0.1 (/) X-Spam-Report: Spam Filtering performed by mx.sourceforge.net. See http://spamassassin.org/tag/ for more details. -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.1 AWL AWL: From: address is in the auto white-list X-Headers-End: 1NhoUL-0003Gh-4e Cc: spi-devel-general@lists.sourceforge.net, yi.li@analog.com, vapier@gentoo.org Subject: [spi-devel-general] [PATCH 2/2] spi/mmc_spi: mmc_spi adaptations for SPI bus locking API X-BeenThere: spi-devel-general@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list List-Id: Linux SPI core/device drivers discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: spi-devel-general-bounces@lists.sourceforge.net X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 17 Feb 2010 18:19:45 +0000 (UTC) diff --git a/drivers/mmc/host/mmc_spi.c b/drivers/mmc/host/mmc_spi.c --- a/drivers/mmc/host/mmc_spi.c +++ b/drivers/mmc/host/mmc_spi.c @@ -181,7 +181,7 @@ mmc_spi_readbytes(struct mmc_spi_host *host, unsigned len) host->data_dma, sizeof(*host->data), DMA_FROM_DEVICE); - status = spi_sync(host->spi, &host->readback); + status = spi_sync_locked(host->spi, &host->readback); if (host->dma_dev) dma_sync_single_for_cpu(host->dma_dev, @@ -540,7 +540,7 @@ mmc_spi_command_send(struct mmc_spi_host *host, host->data_dma, sizeof(*host->data), DMA_BIDIRECTIONAL); } - status = spi_sync(host->spi, &host->m); + status = spi_sync_locked(host->spi, &host->m); if (host->dma_dev) dma_sync_single_for_cpu(host->dma_dev, @@ -684,7 +684,7 @@ mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t, host->data_dma, sizeof(*scratch), DMA_BIDIRECTIONAL); - status = spi_sync(spi, &host->m); + status = spi_sync_locked(spi, &host->m); if (status != 0) { dev_dbg(&spi->dev, "write error (%d)\n", status); @@ -821,7 +821,7 @@ mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t, DMA_FROM_DEVICE); } - status = spi_sync(spi, &host->m); + status = spi_sync_locked(spi, &host->m); if (host->dma_dev) { dma_sync_single_for_cpu(host->dma_dev, @@ -1017,7 +1017,7 @@ mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd, host->data_dma, sizeof(*scratch), DMA_BIDIRECTIONAL); - tmp = spi_sync(spi, &host->m); + tmp = spi_sync_locked(spi, &host->m); if (host->dma_dev) dma_sync_single_for_cpu(host->dma_dev, @@ -1083,6 +1083,9 @@ static void mmc_spi_request(struct mmc_host *mmc, struct mmc_request *mrq) } #endif + /* request exclusive bus access */ + spi_bus_lock(host->spi); + /* issue command; then optionally data and stop */ status = mmc_spi_command_send(host, mrq, mrq->cmd, mrq->data != NULL); if (status == 0 && mrq->data) { @@ -1093,6 +1096,9 @@ static void mmc_spi_request(struct mmc_host *mmc, struct mmc_request *mrq) mmc_cs_off(host); } + /* release the bus */ + spi_bus_unlock(host->spi); + mmc_request_done(host->mmc, mrq); } @@ -1289,23 +1295,6 @@ mmc_spi_detect_irq(int irq, void *mmc) return IRQ_HANDLED; } -struct count_children { - unsigned n; - struct bus_type *bus; -}; - -static int maybe_count_child(struct device *dev, void *c) -{ - struct count_children *ccp = c; - - if (dev->bus == ccp->bus) { - if (ccp->n) - return -EBUSY; - ccp->n++; - } - return 0; -} - static int mmc_spi_probe(struct spi_device *spi) { void *ones; @@ -1337,32 +1326,6 @@ static int mmc_spi_probe(struct spi_device *spi) return status; } - /* We can use the bus safely iff nobody else will interfere with us. - * Most commands consist of one SPI message to issue a command, then - * several more to collect its response, then possibly more for data - * transfer. Clocking access to other devices during that period will - * corrupt the command execution. - * - * Until we have software primitives which guarantee non-interference, - * we'll aim for a hardware-level guarantee. - * - * REVISIT we can't guarantee another device won't be added later... - */ - if (spi->master->num_chipselect > 1) { - struct count_children cc; - - cc.n = 0; - cc.bus = spi->dev.bus; - status = device_for_each_child(spi->dev.parent, &cc, - maybe_count_child); - if (status < 0) { - dev_err(&spi->dev, "can't share SPI bus\n"); - return status; - } - - dev_warn(&spi->dev, "ASSUMING SPI bus stays unshared!\n"); - } - /* We need a supply of ones to transmit. This is the only time * the CPU touches these, so cache coherency isn't a concern. *