From patchwork Fri Jun 28 18:42:36 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hartley Sweeten X-Patchwork-Id: 2801171 Return-Path: X-Original-To: patchwork-spi-devel-general@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 94C159F245 for ; Fri, 28 Jun 2013 19:02:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5ADBB202B4 for ; Fri, 28 Jun 2013 19:02:28 +0000 (UTC) Received: from lists.sourceforge.net (lists.sourceforge.net [216.34.181.88]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2854D202C1 for ; Fri, 28 Jun 2013 19:02:27 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=sfs-ml-1.v29.ch3.sourceforge.com) by sfs-ml-1.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1UsdwA-0007yM-AN; Fri, 28 Jun 2013 19:02:26 +0000 Received: from sog-mx-3.v43.ch3.sourceforge.com ([172.29.43.193] helo=mx.sourceforge.net) by sfs-ml-1.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1Usdw7-0007y5-Ot for spi-devel-general@lists.sourceforge.net; Fri, 28 Jun 2013 19:02:23 +0000 X-ACL-Warn: Received: from mail1.bemta8.messagelabs.com ([216.82.243.206]) by sog-mx-3.v43.ch3.sourceforge.com with esmtps (TLSv1:AES256-SHA:256) (Exim 4.76) id 1Usdw6-0004Va-1Y for spi-devel-general@lists.sourceforge.net; Fri, 28 Jun 2013 19:02:23 +0000 Received: from [216.82.242.115:8233] by server-14.bemta-8.messagelabs.com id 92/8E-02859-E39DDC15; Fri, 28 Jun 2013 18:43:10 +0000 X-Env-Sender: hartleys@visionengravers.com X-Msg-Ref: server-14.tower-132.messagelabs.com!1372444989!11557709!1 X-Originating-IP: [216.166.12.180] X-StarScan-Received: X-StarScan-Version: 6.9.9; banners=-,-,- X-VirusChecked: Checked Received: (qmail 17725 invoked from network); 28 Jun 2013 18:43:10 -0000 Received: from out001.collaborationhost.net (HELO out001.collaborationhost.net) (216.166.12.180) by server-14.tower-132.messagelabs.com with RC4-SHA encrypted SMTP; 28 Jun 2013 18:43:10 -0000 Received: from etch.local (10.2.3.210) by smtp.collaborationhost.net (10.2.0.232) with Microsoft SMTP Server (TLS) id 8.3.213.0; Fri, 28 Jun 2013 13:43:09 -0500 From: H Hartley Sweeten To: Linux Kernel Subject: [PATCH 1/8] spi: spi-ep93xx: use read, write instead of __raw_* variants Date: Fri, 28 Jun 2013 11:42:36 -0700 User-Agent: KMail/1.9.9 MIME-Version: 1.0 Content-Disposition: inline Message-ID: <201306281142.36525.hartleys@visionengravers.com> X-Spam-Score: 0.0 (/) X-Headers-End: 1Usdw6-0004Va-1Y Cc: grant.likely@linaro.org, spi-devel-general@lists.sourceforge.net, mika.westerberg@iki.fi, broonie@kernel.org, Ryan Mallon X-BeenThere: spi-devel-general@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list List-Id: Linux SPI core/device drivers discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: spi-devel-general-bounces@lists.sourceforge.net X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The memory resource used by this driver is ioremap()'d and the normal read,write calls can be used instead of the __raw_* variants. Remove the inline read,write helpers and just do the read,write directly in the callers. Signed-off-by: H Hartley Sweeten Cc: Ryan Mallon Cc: Mika Westerberg Cc: Mark Brown Cc: Grant Likely --- drivers/spi/spi-ep93xx.c | 64 +++++++++++++++--------------------------------- 1 file changed, 20 insertions(+), 44 deletions(-) diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c index d7bac60..c633cd0 100644 --- a/drivers/spi/spi-ep93xx.c +++ b/drivers/spi/spi-ep93xx.c @@ -158,30 +158,6 @@ struct ep93xx_spi_chip { /* converts bits per word to CR0.DSS value */ #define bits_per_word_to_dss(bpw) ((bpw) - 1) -static inline void -ep93xx_spi_write_u8(const struct ep93xx_spi *espi, u16 reg, u8 value) -{ - __raw_writeb(value, espi->regs_base + reg); -} - -static inline u8 -ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg) -{ - return __raw_readb(spi->regs_base + reg); -} - -static inline void -ep93xx_spi_write_u16(const struct ep93xx_spi *espi, u16 reg, u16 value) -{ - __raw_writew(value, espi->regs_base + reg); -} - -static inline u16 -ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg) -{ - return __raw_readw(spi->regs_base + reg); -} - static int ep93xx_spi_enable(const struct ep93xx_spi *espi) { u8 regval; @@ -191,9 +167,9 @@ static int ep93xx_spi_enable(const struct ep93xx_spi *espi) if (err) return err; - regval = ep93xx_spi_read_u8(espi, SSPCR1); + regval = readb(espi->regs_base + SSPCR1); regval |= SSPCR1_SSE; - ep93xx_spi_write_u8(espi, SSPCR1, regval); + writeb(regval, espi->regs_base + SSPCR1); return 0; } @@ -202,9 +178,9 @@ static void ep93xx_spi_disable(const struct ep93xx_spi *espi) { u8 regval; - regval = ep93xx_spi_read_u8(espi, SSPCR1); + regval = readb(espi->regs_base + SSPCR1); regval &= ~SSPCR1_SSE; - ep93xx_spi_write_u8(espi, SSPCR1, regval); + writeb(regval, espi->regs_base + SSPCR1); clk_disable(espi->clk); } @@ -213,18 +189,18 @@ static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi) { u8 regval; - regval = ep93xx_spi_read_u8(espi, SSPCR1); + regval = readb(espi->regs_base + SSPCR1); regval |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); - ep93xx_spi_write_u8(espi, SSPCR1, regval); + writeb(regval, espi->regs_base + SSPCR1); } static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi) { u8 regval; - regval = ep93xx_spi_read_u8(espi, SSPCR1); + regval = readb(espi->regs_base + SSPCR1); regval &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); - ep93xx_spi_write_u8(espi, SSPCR1, regval); + writeb(regval, espi->regs_base + SSPCR1); } /** @@ -437,8 +413,8 @@ static void ep93xx_spi_chip_setup(const struct ep93xx_spi *espi, chip->spi->mode, chip->div_cpsr, chip->div_scr, chip->dss); dev_dbg(&espi->pdev->dev, "setup: cr0 %#x", cr0); - ep93xx_spi_write_u8(espi, SSPCPSR, chip->div_cpsr); - ep93xx_spi_write_u16(espi, SSPCR0, cr0); + writeb(chip->div_cpsr, espi->regs_base + SSPCPSR); + writew(cr0, espi->regs_base + SSPCR0); } static inline int bits_per_word(const struct ep93xx_spi *espi) @@ -456,14 +432,14 @@ static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t) if (t->tx_buf) tx_val = ((u16 *)t->tx_buf)[espi->tx]; - ep93xx_spi_write_u16(espi, SSPDR, tx_val); + writew(tx_val, espi->regs_base + SSPDR); espi->tx += sizeof(tx_val); } else { u8 tx_val = 0; if (t->tx_buf) tx_val = ((u8 *)t->tx_buf)[espi->tx]; - ep93xx_spi_write_u8(espi, SSPDR, tx_val); + writeb(tx_val, espi->regs_base + SSPDR); espi->tx += sizeof(tx_val); } } @@ -473,14 +449,14 @@ static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t) if (bits_per_word(espi) > 8) { u16 rx_val; - rx_val = ep93xx_spi_read_u16(espi, SSPDR); + rx_val = readw(espi->regs_base + SSPDR); if (t->rx_buf) ((u16 *)t->rx_buf)[espi->rx] = rx_val; espi->rx += sizeof(rx_val); } else { u8 rx_val; - rx_val = ep93xx_spi_read_u8(espi, SSPDR); + rx_val = readb(espi->regs_base + SSPDR); if (t->rx_buf) ((u8 *)t->rx_buf)[espi->rx] = rx_val; espi->rx += sizeof(rx_val); @@ -504,7 +480,7 @@ static int ep93xx_spi_read_write(struct ep93xx_spi *espi) struct spi_transfer *t = msg->state; /* read as long as RX FIFO has frames in it */ - while ((ep93xx_spi_read_u8(espi, SSPSR) & SSPSR_RNE)) { + while ((readb(espi->regs_base + SSPSR) & SSPSR_RNE)) { ep93xx_do_read(espi, t); espi->fifo_level--; } @@ -831,14 +807,14 @@ static void ep93xx_spi_process_message(struct ep93xx_spi *espi, * Just to be sure: flush any data from RX FIFO. */ timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT); - while (ep93xx_spi_read_u16(espi, SSPSR) & SSPSR_RNE) { + while (readw(espi->regs_base + SSPSR) & SSPSR_RNE) { if (time_after(jiffies, timeout)) { dev_warn(&espi->pdev->dev, "timeout while flushing RX FIFO\n"); msg->status = -ETIMEDOUT; return; } - ep93xx_spi_read_u16(espi, SSPDR); + readw(espi->regs_base + SSPDR); } /* @@ -917,7 +893,7 @@ static void ep93xx_spi_work(struct work_struct *work) static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id) { struct ep93xx_spi *espi = dev_id; - u8 irq_status = ep93xx_spi_read_u8(espi, SSPIIR); + u8 irq_status = readb(espi->regs_base + SSPIIR); /* * If we got ROR (receive overrun) interrupt we know that something is @@ -925,7 +901,7 @@ static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id) */ if (unlikely(irq_status & SSPIIR_RORIS)) { /* clear the overrun interrupt */ - ep93xx_spi_write_u8(espi, SSPICR, 0); + writeb(0, espi->regs_base + SSPICR); dev_warn(&espi->pdev->dev, "receive overrun, aborting the message\n"); espi->current_msg->status = -EIO; @@ -1111,7 +1087,7 @@ static int ep93xx_spi_probe(struct platform_device *pdev) espi->running = true; /* make sure that the hardware is disabled */ - ep93xx_spi_write_u8(espi, SSPCR1, 0); + writeb(0, espi->regs_base + SSPCR1); error = spi_register_master(master); if (error) {