From patchwork Tue Jul 2 17:09:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hartley Sweeten X-Patchwork-Id: 2814111 Return-Path: X-Original-To: patchwork-spi-devel-general@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A8E429F3C3 for ; Tue, 2 Jul 2013 17:10:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6A81B2018D for ; Tue, 2 Jul 2013 17:10:02 +0000 (UTC) Received: from lists.sourceforge.net (lists.sourceforge.net [216.34.181.88]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2DC3520185 for ; Tue, 2 Jul 2013 17:10:01 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=sfs-ml-4.v29.ch3.sourceforge.com) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1Uu45Y-0000AK-Bk; Tue, 02 Jul 2013 17:10:00 +0000 Received: from sog-mx-4.v43.ch3.sourceforge.com ([172.29.43.194] helo=mx.sourceforge.net) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1Uu45W-0000A7-Pr for spi-devel-general@lists.sourceforge.net; Tue, 02 Jul 2013 17:09:58 +0000 X-ACL-Warn: Received: from mail1.bemta7.messagelabs.com ([216.82.254.106]) by sog-mx-4.v43.ch3.sourceforge.com with esmtps (TLSv1:AES256-SHA:256) (Exim 4.76) id 1Uu45U-0000ho-O8 for spi-devel-general@lists.sourceforge.net; Tue, 02 Jul 2013 17:09:58 +0000 Received: from [216.82.255.3:65302] by server-10.bemta-7.messagelabs.com id B8/7F-03691-F5903D15; Tue, 02 Jul 2013 17:09:51 +0000 X-Env-Sender: hartleys@visionengravers.com X-Msg-Ref: server-13.tower-209.messagelabs.com!1372784990!6331869!1 X-Originating-IP: [216.166.12.98] X-StarScan-Received: X-StarScan-Version: 6.9.9; banners=-,-,- X-VirusChecked: Checked Received: (qmail 5728 invoked from network); 2 Jul 2013 17:09:50 -0000 Received: from out001.collaborationhost.net (HELO out001.collaborationhost.net) (216.166.12.98) by server-13.tower-209.messagelabs.com with RC4-SHA encrypted SMTP; 2 Jul 2013 17:09:50 -0000 Received: from etch.local (10.2.3.210) by smtp.collaborationhost.net (10.2.0.59) with Microsoft SMTP Server (TLS) id 8.3.213.0; Tue, 2 Jul 2013 12:09:50 -0500 From: H Hartley Sweeten To: Linux Kernel Subject: [PATCH v2 07/11] spi: spi-ep93xx: remove 'dss' from per chip private data Date: Tue, 2 Jul 2013 10:09:29 -0700 User-Agent: KMail/1.9.9 MIME-Version: 1.0 Content-Disposition: inline Message-ID: <201307021009.30230.hartleys@visionengravers.com> X-Spam-Score: 0.0 (/) X-Headers-End: 1Uu45U-0000ho-O8 Cc: Ryan Mallon , mika.westerberg@iki.fi, hsweeten@visionengravers.com, broonie@kernel.org, grant.likely@linaro.org, spi-devel-general@lists.sourceforge.net X-BeenThere: spi-devel-general@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list List-Id: Linux SPI core/device drivers discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: spi-devel-general-bounces@lists.sourceforge.net X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This value is only needed to set the bits per word for each transfer of a message. There is no reason to set the value in ep93xx_spi_enable() because ep93xx_spi_process_transfer() sets it again for each transfer. Just pass the t->bits_per_word directly to ep93xx_spi_chip_setup() in ep93xx_spi_process_transfer() and remove 'dss' from the per chip private data. Signed-off-by: H Hartley Sweeten Cc: Ryan Mallon Cc: Mika Westerberg Cc: Mark Brown Cc: Grant Likely Acked-by: Mika Westerberg --- drivers/spi/spi-ep93xx.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c index 34aade1..cc2a240 100644 --- a/drivers/spi/spi-ep93xx.c +++ b/drivers/spi/spi-ep93xx.c @@ -139,7 +139,6 @@ struct ep93xx_spi { * @rate: max rate in hz this chip supports * @div_cpsr: cpsr (pre-scaler) divider * @div_scr: scr divider - * @dss: bits per word (4 - 16 bits) * @ops: private chip operations * * This structure is used to store hardware register specific settings for each @@ -151,7 +150,6 @@ struct ep93xx_spi_chip { unsigned long rate; u8 div_cpsr; u8 div_scr; - u8 dss; struct ep93xx_spi_chip_ops *ops; }; @@ -329,8 +327,6 @@ static int ep93xx_spi_setup(struct spi_device *spi) chip->rate = spi->max_speed_hz; } - chip->dss = bits_per_word_to_dss(spi->bits_per_word); - ep93xx_spi_cs_control(spi, false); return 0; } @@ -407,22 +403,25 @@ static void ep93xx_spi_cleanup(struct spi_device *spi) * ep93xx_spi_chip_setup() - configures hardware according to given @chip * @espi: ep93xx SPI controller struct * @chip: chip specific settings + * @bits_per_word: transfer bits_per_word * * This function sets up the actual hardware registers with settings given in * @chip. Note that no validation is done so make sure that callers validate * settings before calling this. */ static void ep93xx_spi_chip_setup(const struct ep93xx_spi *espi, - const struct ep93xx_spi_chip *chip) + const struct ep93xx_spi_chip *chip, + u8 bits_per_word) { + u8 dss = bits_per_word_to_dss(bits_per_word); u16 cr0; cr0 = chip->div_scr << SSPCR0_SCR_SHIFT; cr0 |= (chip->spi->mode & (SPI_CPHA|SPI_CPOL)) << SSPCR0_MODE_SHIFT; - cr0 |= chip->dss; + cr0 |= dss; dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n", - chip->spi->mode, chip->div_cpsr, chip->div_scr, chip->dss); + chip->spi->mode, chip->div_cpsr, chip->div_scr, dss); dev_dbg(&espi->pdev->dev, "setup: cr0 %#x", cr0); ep93xx_spi_write_u8(espi, SSPCPSR, chip->div_cpsr); @@ -709,9 +708,7 @@ static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi, return; } - chip->dss = bits_per_word_to_dss(t->bits_per_word); - - ep93xx_spi_chip_setup(espi, chip); + ep93xx_spi_chip_setup(espi, chip, t->bits_per_word); espi->rx = 0; espi->tx = 0;