From patchwork Tue Oct 1 20:15:47 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Trent Piepho X-Patchwork-Id: 2971991 Return-Path: X-Original-To: patchwork-spi-devel-general@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7B8E8BFF0B for ; Tue, 1 Oct 2013 20:15:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B2AA1201C4 for ; Tue, 1 Oct 2013 20:15:54 +0000 (UTC) Received: from lists.sourceforge.net (lists.sourceforge.net [216.34.181.88]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9B1C120423 for ; Tue, 1 Oct 2013 20:15:53 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=sfs-ml-2.v29.ch3.sourceforge.com) by sfs-ml-2.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1VR6ML-0001IH-1U; Tue, 01 Oct 2013 20:15:53 +0000 Received: from sog-mx-3.v43.ch3.sourceforge.com ([172.29.43.193] helo=mx.sourceforge.net) by sfs-ml-2.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1VR6MJ-0001I3-9G for spi-devel-general@lists.sourceforge.net; Tue, 01 Oct 2013 20:15:51 +0000 Received-SPF: pass (sog-mx-3.v43.ch3.sourceforge.com: domain of gmail.com designates 209.85.192.169 as permitted sender) client-ip=209.85.192.169; envelope-from=tpiepho@gmail.com; helo=mail-pd0-f169.google.com; Received: from mail-pd0-f169.google.com ([209.85.192.169]) by sog-mx-3.v43.ch3.sourceforge.com with esmtps (TLSv1:RC4-SHA:128) (Exim 4.76) id 1VR6MG-0000FX-NG for spi-devel-general@lists.sourceforge.net; Tue, 01 Oct 2013 20:15:51 +0000 Received: by mail-pd0-f169.google.com with SMTP id r10so7786762pdi.0 for ; Tue, 01 Oct 2013 13:15:42 -0700 (PDT) X-Received: by 10.66.152.102 with SMTP id ux6mr5637142pab.79.1380658542845; Tue, 01 Oct 2013 13:15:42 -0700 (PDT) Received: from [127.0.1.1] (174-31-223-101.tukw.qwest.net. [174.31.223.101]) by mx.google.com with ESMTPSA id im8sm8564974pbc.24.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 01 Oct 2013 13:15:42 -0700 (PDT) Subject: [PATCH 12/13] spi: spi-mxs: Don't set clock for each xfer To: spi-devel-general@lists.sourceforge.net, Mark Brown From: Trent Piepho Date: Tue, 01 Oct 2013 13:15:47 -0700 Message-ID: <20131001201547.13660.33199.stgit@Graphine> In-Reply-To: <20131001201425.13660.72740.stgit@Graphine> References: <20131001201425.13660.72740.stgit@Graphine> User-Agent: StGit/0.15 MIME-Version: 1.0 X-Spam-Score: -1.6 (-) X-Headers-End: 1VR6MG-0000FX-NG Cc: Marek Vasut , Fabio Estevam , Shawn Guo X-BeenThere: spi-devel-general@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list List-Id: Linux SPI core/device drivers discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: spi-devel-general-bounces@lists.sourceforge.net X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, FREEMAIL_FROM,RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP mxs_spi_setup_transfer() would set the SSP SCK rate every time it was called, which is before every transfer. It is uncommon for the SCK rate to change between transfers (or at all of that matter) and this causes many unnecessary reprogrammings of the clock registers. Code changed to only set the rate when it changes. This significantly speeds up short SPI messages, especially messages made up of many transfers, as the calculation of the clock divisors is rather costly. On an iMX287, using spidev with messages that consist of 511 transfers of 4 bytes each at an SCK of 48 MHz, the effective transfer rate more than doubles from about 290 KB/sec to 600 KB/sec! Signed-off-by: Trent Piepho Cc: Marek Vasut Cc: Fabio Estevam Cc: Shawn Guo --- drivers/spi/spi-mxs.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) ------------------------------------------------------------------------------ October Webinars: Code for Performance Free Intel webinars can help you accelerate application performance. Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from the latest Intel processors and coprocessors. See abstracts and register > http://pubads.g.doubleclick.net/gampad/clk?id=60134791&iu=/4140/ostg.clktrk diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c index 9e6101a..759de70 100644 --- a/drivers/spi/spi-mxs.c +++ b/drivers/spi/spi-mxs.c @@ -67,6 +67,7 @@ struct mxs_spi { struct mxs_ssp ssp; struct completion c; + unsigned int sck; /* Rate requested (vs actual) */ }; static int mxs_spi_setup_transfer(struct spi_device *dev, @@ -81,7 +82,19 @@ static int mxs_spi_setup_transfer(struct spi_device *dev, return -EINVAL; } - mxs_ssp_set_clk_rate(ssp, hz); + if (hz != spi->sck) { + mxs_ssp_set_clk_rate(ssp, hz); + /* + * Save requested rate, hz, rather than the actual rate, + * ssp->clk_rate. Otherwise we would set the rate every trasfer + * when the actual rate is not quite the same as requested rate. + */ + spi->sck = hz; + /* + * Perhaps we should return an error if the actual clock is + * nowhere close to what was requested? + */ + } writel(BM_SSP_CTRL0_LOCK_CS, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);