From patchwork Thu Dec 1 10:27:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 9455765 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 43F7F60756 for ; Thu, 1 Dec 2016 10:28:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 30A2E284CB for ; Thu, 1 Dec 2016 10:28:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 257DA284CF; Thu, 1 Dec 2016 10:28:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C9414284CE for ; Thu, 1 Dec 2016 10:28:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756676AbcLAK2K (ORCPT ); Thu, 1 Dec 2016 05:28:10 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:54099 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756532AbcLAK2I (ORCPT ); Thu, 1 Dec 2016 05:28:08 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id A7C1221CFE; Thu, 1 Dec 2016 11:27:32 +0100 (CET) Received: from latitudeE7470 (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 88E3B20432; Thu, 1 Dec 2016 11:27:32 +0100 (CET) From: Romain Perier To: Mark Brown , linux-spi@vger.kernel.org Cc: Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , devicetree@vger.kernel.org, Rob Herring , Ian Campbell , Pawel Moll , Mark Rutland , Kumar Gala , linux-arm-kernel@lists.infradead.org, Thomas Petazzoni , Nadav Haklai , xigu@marvell.com, dingwei@marvell.com Subject: [PATCH v3 4/5] arm64: dts: marvell: Add definition of SPI controller for Armada 3700 Date: Thu, 1 Dec 2016 11:27:18 +0100 Message-Id: <20161201102719.4291-5-romain.perier@free-electrons.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20161201102719.4291-1-romain.perier@free-electrons.com> References: <20161201102719.4291-1-romain.perier@free-electrons.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Armada 3700 SoC has an SPI Controller, this commit adds the definition of the SPI device node at the SoC level. Signed-off-by: Romain Perier Tested-by: Gregory CLEMENT --- Changes in v3: - Fixed wrong register size for spi0, as suggested by the maintainer on the ML. - Added tag "Tested-by" by Gregory Changes in v2: - Removed properties max-frequency and clock-frequency, it is no longer required and not used by the DT-bindings. arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index e9bd587..fcef9a5 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -98,6 +98,17 @@ /* 32M internal register @ 0xd000_0000 */ ranges = <0x0 0x0 0xd0000000 0x2000000>; + spi0: spi@10600 { + compatible = "marvell,armada-3700-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10600 0xA00>; + clocks = <&nb_periph_clk 7>; + interrupts = ; + num-cs = <4>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "marvell,armada-3700-uart"; reg = <0x12000 0x400>;