From patchwork Tue May 23 04:03:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 9741879 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 40F1D6032B for ; Tue, 23 May 2017 04:03:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2B41C28380 for ; Tue, 23 May 2017 04:03:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1EEBF28793; Tue, 23 May 2017 04:03:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6A3FF28792 for ; Tue, 23 May 2017 04:03:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760855AbdEWEDd (ORCPT ); Tue, 23 May 2017 00:03:33 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:46155 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760872AbdEWEDc (ORCPT ); Tue, 23 May 2017 00:03:32 -0400 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 2773D806A8; Tue, 23 May 2017 16:03:30 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail; t=1495512210; bh=X+OQcnKRzGlmxIFLejf9/WNWEPW+EoY/CJZQuB+/Mts=; h=From:To:Cc:Subject:Date; b=SG8nq5wpezLEby64utYGploUcNnBUP4be85VzAh0hCDLoZL9nc7b/T/AdJ+AH/0mU tEOgzsEtqHDrmNhzd4LHl2KQ7XkI+DG+dkl6agQWJwwks3h0C+tkEenaiODuLcvqTh dmuqU2p5zrIrOlsRt3gc2afvbYOw8cwj0bOjrW4M= Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7, 5, 7, 9061) id ; Tue, 23 May 2017 16:03:30 +1200 Received: from chrisp-dl.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by smtp (Postfix) with ESMTP id 938C013EC73; Tue, 23 May 2017 16:03:31 +1200 (NZST) Received: by chrisp-dl.atlnz.lc (Postfix, from userid 1030) id 7AAE41E1D4A; Tue, 23 May 2017 16:03:29 +1200 (NZST) From: Chris Packham To: broonie@kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Chris Packham Subject: [PATCH 1/2] spi: orion: Handle GPIO chip-selects Date: Tue, 23 May 2017 16:03:21 +1200 Message-Id: <20170523040322.10433-1-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.13.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some hardware designs use GPIOs to add (or supplement) the SPI chip-select so that more than one SPI slave device can be used. For this to work with the spi-orion driver the SPI_MASTER_GPIO_SS flag needs to be set (because the other outputs are gated internally by the CS) and the correct chip-select (in this case CS0) needs to be driven by the controller. Signed-off-by: Chris Packham --- drivers/spi/spi-orion.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c index be2e87ee8b31..28fc9f161b9d 100644 --- a/drivers/spi/spi-orion.c +++ b/drivers/spi/spi-orion.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #define DRIVER_NAME "orion_spi" @@ -320,12 +321,18 @@ orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) static void orion_spi_set_cs(struct spi_device *spi, bool enable) { struct orion_spi *orion_spi; + int cs; + + if (gpio_is_valid(spi->cs_gpio)) + cs = 0; + else + cs = spi->chip_select; orion_spi = spi_master_get_devdata(spi->master); orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK); orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, - ORION_SPI_CS(spi->chip_select)); + ORION_SPI_CS(cs)); /* Chip select logic is inverted from spi_set_cs */ if (!enable) @@ -606,6 +613,7 @@ static int orion_spi_probe(struct platform_device *pdev) master->setup = orion_spi_setup; master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); master->auto_runtime_pm = true; + master->flags = SPI_MASTER_GPIO_SS; platform_set_drvdata(pdev, master);