From patchwork Tue Nov 28 13:29:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yixun Lan X-Patchwork-Id: 10080321 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7068F6056A for ; Tue, 28 Nov 2017 13:29:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5B38E288EC for ; Tue, 28 Nov 2017 13:29:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4BAB828756; Tue, 28 Nov 2017 13:29:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2E1F8281E1 for ; Tue, 28 Nov 2017 13:29:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753062AbdK1N3n (ORCPT ); Tue, 28 Nov 2017 08:29:43 -0500 Received: from mail-sh2.amlogic.com ([58.32.228.45]:47649 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751807AbdK1N3b (ORCPT ); Tue, 28 Nov 2017 08:29:31 -0500 Received: from localhost.localdomain (10.18.20.164) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server id 15.0.1320.4; Tue, 28 Nov 2017 21:28:55 +0800 From: Yixun Lan To: Kevin Hilman , CC: Mark Brown , , Neil Armstrong , Jerome Brunet , Rob Herring , Mark Rutland , Carlo Caione , Yixun Lan , Sunny Luo , , , Subject: [PATCH 3/3] ARM64: dts: meson-axg: add the SPICC controller Date: Tue, 28 Nov 2017 21:29:26 +0800 Message-ID: <20171128132926.19051-4-yixun.lan@amlogic.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171128132926.19051-1-yixun.lan@amlogic.com> References: <20171128132926.19051-1-yixun.lan@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.20.164] Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sunny Luo Add DT info for the SPICC controller which found in the Amlogic's Meson-AXG SoC. Signed-off-by: Sunny Luo Signed-off-by: Yixun Lan --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 92 ++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index fe3878f7718c..021b929d8d6e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -208,6 +208,28 @@ interrupts = ; status = "disabled"; }; + + spicc_a: spi@13000 { + compatible = "amlogic,meson-axg-spicc"; + reg = <0x0 0x13000 0x0 0x3c>; + interrupts = ; + clocks = <&clkc CLKID_SPICC0>; + clock-names = "core"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spicc_b: spi@15000 { + compatible = "amlogic,meson-axg-spicc"; + reg = <0x0 0x15000 0x0 0x3c>; + interrupts = ; + clocks = <&clkc CLKID_SPICC1>; + clock-names = "core"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; gic: interrupt-controller@ffc01000 { @@ -470,6 +492,76 @@ function = "pwm_d"; }; }; + + spi_a_pins: spi_a { + mux { + groups = "spi_miso_a", + "spi_mosi_a", + "spi_clk_a"; + function = "spi_a"; + }; + }; + + spi_ss0_a_pins: spi_ss0_a { + mux { + groups = "spi_ss0_a"; + function = "spi_a"; + }; + }; + + spi_ss1_a_pins: spi_ss1_a { + mux { + groups = "spi_ss1_a"; + function = "spi_a"; + }; + }; + + spi_ss2_a_pins: spi_ss2_a { + mux { + groups = "spi_ss2_a"; + function = "spi_a"; + }; + }; + + + spi_b_a_pins: spi_b_a { + mux { + groups = "spi_miso_b_a", + "spi_mosi_b_a", + "spi_clk_b_a"; + function = "spi_b"; + }; + }; + + spi_ss0_b_a_pins: spi_ss0_b_a { + mux { + groups = "spi_ss0_b_a"; + function = "spi_b"; + }; + }; + + spi_ss1_b_pins: spi_ss1_b { + mux { + groups = "spi_ss1_b"; + function = "spi_b"; + }; + }; + + spi_b_x_pins: spi_b_x { + mux { + groups = "spi_miso_b_x", + "spi_mosi_b_x", + "spi_clk_b_x"; + function = "spi_b"; + }; + }; + + spi_ss0_b_x_pins: spi_ss0_b_x { + mux { + groups = "spi_ss0_b_x"; + function = "spi_b"; + }; + }; }; };