From patchwork Fri Jun 1 13:13:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boris Brezillon X-Patchwork-Id: 10443401 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 76EB0602BD for ; Fri, 1 Jun 2018 13:14:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 69DFC28D5E for ; Fri, 1 Jun 2018 13:14:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5DFA628D7B; Fri, 1 Jun 2018 13:14:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E3AE528D79 for ; Fri, 1 Jun 2018 13:14:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751788AbeFANOV (ORCPT ); Fri, 1 Jun 2018 09:14:21 -0400 Received: from mail.bootlin.com ([62.4.15.54]:53330 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751378AbeFANOU (ORCPT ); Fri, 1 Jun 2018 09:14:20 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id 7C9B320702; Fri, 1 Jun 2018 15:14:18 +0200 (CEST) Received: from localhost.localdomain (AAubervilliers-681-1-125-111.w90-88.abo.wanadoo.fr [90.88.63.111]) by mail.bootlin.com (Postfix) with ESMTPSA id 253FC20726; Fri, 1 Jun 2018 15:14:08 +0200 (CEST) From: Boris Brezillon To: David Woodhouse , Brian Norris , Boris Brezillon , Marek Vasut , Richard Weinberger , linux-mtd@lists.infradead.org, Miquel Raynal , Mark Brown , linux-spi@vger.kernel.org, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , devicetree@vger.kernel.org Subject: [PATCH v8 2/4] dt-bindings: Add bindings for SPI NAND devices Date: Fri, 1 Jun 2018 15:13:58 +0200 Message-Id: <20180601131400.17634-3-boris.brezillon@bootlin.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180601131400.17634-1-boris.brezillon@bootlin.com> References: <20180601131400.17634-1-boris.brezillon@bootlin.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add bindings for SPI NAND chips. Signed-off-by: Boris Brezillon --- Changes in v8: - Fixed a typo in the commit message --- Documentation/devicetree/bindings/mtd/spi-nand.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/spi-nand.txt diff --git a/Documentation/devicetree/bindings/mtd/spi-nand.txt b/Documentation/devicetree/bindings/mtd/spi-nand.txt new file mode 100644 index 000000000000..d55f80196c63 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/spi-nand.txt @@ -0,0 +1,27 @@ +SPI NAND flash + +Required properties: +- compatible: should be "spi-nand" +- reg: should encode the chip-select line used to access the NAND chip + +Optional properties +- spi-max-frequency: maximum frequency of the SPI bus the chip can operate at. + This should encode board limitations (i.e. max freq can't + be achieved due to crosstalk on IO lines). + When unspecified, the driver assumes the chip can run at + the max frequency defined in the spec (information + extracted chip detection time). +- spi-tx-bus-width: The bus width (number of data wires) that is used for MOSI. + Only encodes the board constraints (i.e. when not all IO + signals are routed on the board). Device constraints are + extracted when detecting the chip, and controller + constraints are exposed by the SPI mem controller. If this + property is missing that means no constraint at the board + level. +- spi-rx-bus-width: The bus width (number of data wires) that is used for MISO. + Only encodes the board constraints (i.e. when not all IO + signals are routed on the board). Device constraints are + extracted when detecting the chip, and controller + constraints are exposed by the SPI mem controller. If this + property is missing that means no constraint at the board + level.