From patchwork Sun Jul 22 21:20:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 10539421 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A778B1823 for ; Sun, 22 Jul 2018 21:20:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 943C12843B for ; Sun, 22 Jul 2018 21:20:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 87C2E28449; Sun, 22 Jul 2018 21:20:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2ACB72843B for ; Sun, 22 Jul 2018 21:20:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387772AbeGVWS0 (ORCPT ); Sun, 22 Jul 2018 18:18:26 -0400 Received: from mx2.suse.de ([195.135.220.15]:38804 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2387794AbeGVWSZ (ORCPT ); Sun, 22 Jul 2018 18:18:25 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay1.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 91399AFD6; Sun, 22 Jul 2018 21:20:23 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-mips@linux-mips.org Cc: Ralf Baechle , Paul Burton , James Hogan , linux-kernel@vger.kernel.org, Ionela Voinescu , =?utf-8?q?Andreas_F=C3=A4rber?= , Mark Brown , linux-spi@vger.kernel.org Subject: [PATCH 13/15] spi: img-spfi: RX maximum burst size for DMA is 8 Date: Sun, 22 Jul 2018 23:20:08 +0200 Message-Id: <20180722212010.3979-14-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20180722212010.3979-1-afaerber@suse.de> References: <20180722212010.3979-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ionela Voinescu The depth of the FIFOs is 16 bytes. The DMA request line is tied to the half full/empty (depending on the use of the TX or RX FIFO) threshold. For the TX FIFO, if you set a burst size of 8 (equal to half the depth) the first burst goes into FIFO without any issues, but due the latency involved (the time the data leaves the DMA engine to the time it arrives at the FIFO), the DMA might trigger another burst of 8. But given that there is no space for 2 additonal bursts of 8, this would result in a failure. Therefore, we have to keep the burst size for TX to 4 to accomodate for an extra burst. For the read (RX) scenario, the DMA request line goes high when there is at least 8 entries in the FIFO (half full), and we can program the burst size to be 8 because the risk of accidental burst does not exist. The DMA engine will not trigger another read until the read data for all the burst it has sent out has been received. While here, move the burst size setting outside of the if/else branches as they have the same value for both 8 and 32 bit data widths. Signed-off-by: Ionela Voinescu Signed-off-by: Andreas Färber --- drivers/spi/spi-img-spfi.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c index 231b59c1ab60..8ad6c75d0af5 100644 --- a/drivers/spi/spi-img-spfi.c +++ b/drivers/spi/spi-img-spfi.c @@ -346,12 +346,11 @@ static int img_spfi_start_dma(struct spi_master *master, if (xfer->len % 4 == 0) { rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA; rxconf.src_addr_width = 4; - rxconf.src_maxburst = 4; } else { rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA; rxconf.src_addr_width = 1; - rxconf.src_maxburst = 4; } + rxconf.src_maxburst = 8; dmaengine_slave_config(spfi->rx_ch, &rxconf); rxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl, @@ -370,12 +369,11 @@ static int img_spfi_start_dma(struct spi_master *master, if (xfer->len % 4 == 0) { txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA; txconf.dst_addr_width = 4; - txconf.dst_maxburst = 4; } else { txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA; txconf.dst_addr_width = 1; - txconf.dst_maxburst = 4; } + txconf.dst_maxburst = 4; dmaengine_slave_config(spfi->tx_ch, &txconf); txdesc = dmaengine_prep_slave_sg(spfi->tx_ch, xfer->tx_sg.sgl,