From patchwork Fri Jul 27 19:53:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Belloni X-Patchwork-Id: 10547687 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B91C71751 for ; Fri, 27 Jul 2018 19:55:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A936B294CF for ; Fri, 27 Jul 2018 19:55:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9CD112BB07; Fri, 27 Jul 2018 19:55:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 46D22294CF for ; Fri, 27 Jul 2018 19:55:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389415AbeG0VSV (ORCPT ); Fri, 27 Jul 2018 17:18:21 -0400 Received: from mail.bootlin.com ([62.4.15.54]:46742 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389395AbeG0VSV (ORCPT ); Fri, 27 Jul 2018 17:18:21 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id 4CF3320943; Fri, 27 Jul 2018 21:54:55 +0200 (CEST) Received: from localhost (unknown [88.191.26.124]) by mail.bootlin.com (Postfix) with ESMTPSA id 92808209D8; Fri, 27 Jul 2018 21:53:59 +0200 (CEST) From: Alexandre Belloni To: Mark Brown , James Hogan Cc: Paul Burton , Andy Shevchenko , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Thomas Petazzoni , Allan Nielsen , Alexandre Belloni , Rob Herring Subject: [PATCH v3 2/5] dt-bindings: spi: snps,dw-apb-ssi: document Microsemi integration Date: Fri, 27 Jul 2018 21:53:55 +0200 Message-Id: <20180727195358.23336-3-alexandre.belloni@bootlin.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180727195358.23336-1-alexandre.belloni@bootlin.com> References: <20180727195358.23336-1-alexandre.belloni@bootlin.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The integration of the Designware SPI controller on Microsemi SoCs requires an extra register set to be able to give the IP control of the SPI interface. Cc: Rob Herring Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index 204b311e0400..d97b9fc4c1cb 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -1,8 +1,9 @@ Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface. Required properties: -- compatible : "snps,dw-apb-ssi" -- reg : The register base for the controller. +- compatible : "snps,dw-apb-ssi" or "mscc,-spi" +- reg : The register base for the controller. For "mscc,-spi", a second + register set is required (named ICPU_CFG:SPI_MST) - interrupts : One interrupt, used by the controller. - #address-cells : <1>, as required by generic SPI binding. - #size-cells : <0>, also as required by generic SPI binding.