@@ -200,6 +200,9 @@ static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t ofs,
/* convert the dummy cycles to the number of bytes */
op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
+ if (nor->read_proto & SNOR_PROTO_INST_2BYTE)
+ op.cmd.nbytes = 2;
+
spi_nor_adjust_op(nor, &op);
while (remaining) {
@@ -258,6 +261,9 @@ static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t ofs,
op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
+ if (nor->write_proto & SNOR_PROTO_INST_2BYTE)
+ op.cmd.nbytes = 2;
+
if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
op.addr.nbytes = 0;
@@ -2433,13 +2439,13 @@ static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor)
struct spi_nor_read_command {
u8 num_mode_clocks;
u8 num_wait_states;
- u8 opcode;
- enum spi_nor_protocol proto;
+ u16 opcode;
+ u32 proto;
};
struct spi_nor_pp_command {
- u8 opcode;
- enum spi_nor_protocol proto;
+ u16 opcode;
+ u32 proto;
};
enum spi_nor_read_command_index {
@@ -2499,8 +2505,7 @@ static void
spi_nor_set_read_settings(struct spi_nor_read_command *read,
u8 num_mode_clocks,
u8 num_wait_states,
- u8 opcode,
- enum spi_nor_protocol proto)
+ u16 opcode, u32 proto)
{
read->num_mode_clocks = num_mode_clocks;
read->num_wait_states = num_wait_states;
@@ -2510,8 +2515,7 @@ spi_nor_set_read_settings(struct spi_nor_read_command *read,
static void
spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
- u8 opcode,
- enum spi_nor_protocol proto)
+ u16 opcode, u32 proto)
{
pp->opcode = opcode;
pp->proto = proto;
@@ -2887,6 +2891,9 @@ static int spi_nor_spimem_check_readop(struct spi_nor *nor,
op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) *
op.dummy.buswidth / 8;
+ if (read->proto & SNOR_PROTO_INST_2BYTE)
+ op.cmd.nbytes = 2;
+
/*
* First test with 3 address bytes. The opcode itself might already
* be a 4B addressing opcode but we don't care, because SPI controller
@@ -2915,6 +2922,9 @@ static int spi_nor_spimem_check_progop(struct spi_nor *nor,
op.addr.buswidth = spi_nor_get_protocol_addr_nbits(pp->proto);
op.data.buswidth = spi_nor_get_protocol_data_nbits(pp->proto);
+ if (pp->proto & SNOR_PROTO_INST_2BYTE)
+ op.cmd.nbytes = 2;
+
/*
* First test with 3 address bytes. The opcode itself might already
* be a 4B addressing opcode but we don't care, because SPI controller
@@ -166,6 +166,8 @@
#define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
+#define SNOR_PROTO_INST_2BYTE BIT(31)
+
#define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
(SNOR_PROTO_INST(_inst_nbits) | \
SNOR_PROTO_ADDR(_addr_nbits) | \
When operating in octo mode we might have to use 2byte opcodes. Patch struct spi_nor_{read,pp}_command to take that into account. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> --- drivers/mtd/spi-nor/spi-nor.c | 26 ++++++++++++++++++-------- include/linux/mtd/spi-nor.h | 2 ++ 2 files changed, 20 insertions(+), 8 deletions(-)