From patchwork Fri Oct 12 08:48:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boris Brezillon X-Patchwork-Id: 10638081 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3CFDF1508 for ; Fri, 12 Oct 2018 08:49:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2C1DC2B742 for ; Fri, 12 Oct 2018 08:49:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 20E1A2B75D; Fri, 12 Oct 2018 08:49:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A97342B742 for ; Fri, 12 Oct 2018 08:49:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728004AbeJLQUY (ORCPT ); Fri, 12 Oct 2018 12:20:24 -0400 Received: from mail.bootlin.com ([62.4.15.54]:43167 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727952AbeJLQUX (ORCPT ); Fri, 12 Oct 2018 12:20:23 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id 2B2E2207BF; Fri, 12 Oct 2018 10:48:58 +0200 (CEST) Received: from localhost.localdomain (AAubervilliers-681-1-7-245.w90-88.abo.wanadoo.fr [90.88.129.245]) by mail.bootlin.com (Postfix) with ESMTPSA id 1727D20DD2; Fri, 12 Oct 2018 10:48:31 +0200 (CEST) From: Boris Brezillon To: David Woodhouse , Brian Norris , Boris Brezillon , Marek Vasut , Richard Weinberger , linux-mtd@lists.infradead.org, Yogesh Gaur , Vignesh R , Cyrille Pitchen Cc: Julien Su , Mason Yang , , Mark Brown , linux-spi@vger.kernel.org Subject: [PATCH RFC 11/18] mtd: spi-nor: Prepare things for 2byte opcodes Date: Fri, 12 Oct 2018 10:48:18 +0200 Message-Id: <20181012084825.23697-12-boris.brezillon@bootlin.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20181012084825.23697-1-boris.brezillon@bootlin.com> References: <20181012084825.23697-1-boris.brezillon@bootlin.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When operating in octo mode we might have to use 2byte opcodes. Patch struct spi_nor_{read,pp}_command to take that into account. Signed-off-by: Boris Brezillon --- drivers/mtd/spi-nor/spi-nor.c | 26 ++++++++++++++++++-------- include/linux/mtd/spi-nor.h | 2 ++ 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 33a07d9eb7a8..86625f1e25b3 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -200,6 +200,9 @@ static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t ofs, /* convert the dummy cycles to the number of bytes */ op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; + if (nor->read_proto & SNOR_PROTO_INST_2BYTE) + op.cmd.nbytes = 2; + spi_nor_adjust_op(nor, &op); while (remaining) { @@ -258,6 +261,9 @@ static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t ofs, op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto); op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto); + if (nor->write_proto & SNOR_PROTO_INST_2BYTE) + op.cmd.nbytes = 2; + if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) op.addr.nbytes = 0; @@ -2433,13 +2439,13 @@ static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor) struct spi_nor_read_command { u8 num_mode_clocks; u8 num_wait_states; - u8 opcode; - enum spi_nor_protocol proto; + u16 opcode; + u32 proto; }; struct spi_nor_pp_command { - u8 opcode; - enum spi_nor_protocol proto; + u16 opcode; + u32 proto; }; enum spi_nor_read_command_index { @@ -2499,8 +2505,7 @@ static void spi_nor_set_read_settings(struct spi_nor_read_command *read, u8 num_mode_clocks, u8 num_wait_states, - u8 opcode, - enum spi_nor_protocol proto) + u16 opcode, u32 proto) { read->num_mode_clocks = num_mode_clocks; read->num_wait_states = num_wait_states; @@ -2510,8 +2515,7 @@ spi_nor_set_read_settings(struct spi_nor_read_command *read, static void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, - u8 opcode, - enum spi_nor_protocol proto) + u16 opcode, u32 proto) { pp->opcode = opcode; pp->proto = proto; @@ -2887,6 +2891,9 @@ static int spi_nor_spimem_check_readop(struct spi_nor *nor, op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) * op.dummy.buswidth / 8; + if (read->proto & SNOR_PROTO_INST_2BYTE) + op.cmd.nbytes = 2; + /* * First test with 3 address bytes. The opcode itself might already * be a 4B addressing opcode but we don't care, because SPI controller @@ -2915,6 +2922,9 @@ static int spi_nor_spimem_check_progop(struct spi_nor *nor, op.addr.buswidth = spi_nor_get_protocol_addr_nbits(pp->proto); op.data.buswidth = spi_nor_get_protocol_data_nbits(pp->proto); + if (pp->proto & SNOR_PROTO_INST_2BYTE) + op.cmd.nbytes = 2; + /* * First test with 3 address bytes. The opcode itself might already * be a 4B addressing opcode but we don't care, because SPI controller diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index f80aba464eb2..5b0045720049 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -166,6 +166,8 @@ #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */ +#define SNOR_PROTO_INST_2BYTE BIT(31) + #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \ (SNOR_PROTO_INST(_inst_nbits) | \ SNOR_PROTO_ADDR(_addr_nbits) | \