@@ -52,6 +52,7 @@
#define CR_RTF BIT(8)
#define CR_RST BIT(1)
#define CR_MEN BIT(0)
+#define SR_MBF BIT(24)
#define SR_TCF BIT(10)
#define SR_FCF BIT(9)
#define SR_RDF BIT(1)
@@ -65,6 +66,7 @@
#define CFGR1_PCSPOL BIT(8)
#define CFGR1_NOSTALL BIT(3)
#define CFGR1_MASTER BIT(0)
+#define FSR_RXCOUNT (BIT(16)|BIT(17)|BIT(18))
#define RSR_RXEMPTY BIT(1)
#define TCR_CPOL BIT(31)
#define TCR_CPHA BIT(30)
@@ -446,6 +448,13 @@ static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
return IRQ_HANDLED;
}
+ if (temp_SR & SR_MBF ||
+ readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_RXCOUNT) {
+ writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
+ fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
+ return IRQ_HANDLED;
+ }
+
if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
complete(&fsl_lpspi->xfer_done);
Add judgment on SR_MBF and FSR_RXCOUNT. In PIO mode, if don't use CONT to keep cs selected in one transfer, the transfer will go wrong. FCIE will be set after one frame transfer finish. If use CONT, the frame refer to the whole data in one transfer. If don't use CONT, the frame refer to one byte of whole data. This will cause the transfer ending early. This patch add a register reading in isr function, it might lead to a slight decrease in the max transmission speed in PIO mode. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> --- drivers/spi/spi-fsl-lpspi.c | 9 +++++++++ 1 file changed, 9 insertions(+)