From patchwork Tue Jan 29 01:55:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 10785321 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0AF1213B5 for ; Tue, 29 Jan 2019 01:56:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F0BDE2AD5E for ; Tue, 29 Jan 2019 01:56:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E507C2AD6D; Tue, 29 Jan 2019 01:56:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 915512AD5E for ; Tue, 29 Jan 2019 01:56:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727290AbfA2B4Q (ORCPT ); Mon, 28 Jan 2019 20:56:16 -0500 Received: from mail-pf1-f196.google.com ([209.85.210.196]:43625 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727283AbfA2Bzx (ORCPT ); Mon, 28 Jan 2019 20:55:53 -0500 Received: by mail-pf1-f196.google.com with SMTP id w73so8878848pfk.10 for ; Mon, 28 Jan 2019 17:55:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cATQLWSVRvCn1SsUsbBtXSPozOZ5/uzoCaTY1Z0hItQ=; b=GrLPu896AeP69/qFFjVidbQpr5XsvKSqPGrnRkFqc0oyA9QDbdjOHOPxiOrpxnDspk ujGr5qnUHvn0y9mrC7dvRk6mcug7rRaPPlDcQn3vJlaDQMgoHhqrMmbz84SNzPiUZOg8 mZ+6PRL5tDD3Tg39o0KMTzuUf8UtF7d7cX0C8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cATQLWSVRvCn1SsUsbBtXSPozOZ5/uzoCaTY1Z0hItQ=; b=CcQVnkxFalGOJ7dmnn57/RI22IpYvf3uq5Xph6gkCIFv2RcQcXBIezi61/aWQ6JOQ5 dRBgNM3ey5CujPbyCvGKvePqUQtBx2slG/mVKTNgLhsw+0hq6ixA07z/z+OooLxl5yjw icCt5zSJsBT/8sraYskFx4kBElKEAL0qef3qDWjisTHBloBVyJyEP8HjYDl68WuHsTOJ KvjR9aTMzf2kk4ZdOM3cDeZe2D/uu6aKi5sT6oBZ7onwNytt0GbHqVhIJqVi+rELFy7s gGj5hCqa3ZIK7kmAcZUSOmFOcVwdWWE5src3Pyg8Qsb64JscZWqrrF+imFKHt81r55gr 0HjQ== X-Gm-Message-State: AJcUukeLeQi8xtColhhk9A9wmJM1CajfS2HfPWpScsX6IYSg3UQk/oIW I0gK8pXTRfxE6o/C9wLsQ9bbDg== X-Google-Smtp-Source: ALg8bN6gGuF6SvKMeUDruFsteW+0NOW13owtLSEFBvqKNcngSC2ynmws9guSkqqGCxHQYsIW+FN+Pw== X-Received: by 2002:a65:64c8:: with SMTP id t8mr21686546pgv.31.1548726952920; Mon, 28 Jan 2019 17:55:52 -0800 (PST) Received: from smtp.gmail.com ([2620:15c:202:1:fa53:7765:582b:82b9]) by smtp.gmail.com with ESMTPSA id g15sm142911530pfj.131.2019.01.28.17.55.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 17:55:52 -0800 (PST) From: Stephen Boyd To: linux-kernel@vger.kernel.org Cc: Rajendra Nayak , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, Ulf Hansson , Viresh Kumar , Doug Anderson Subject: [RFC/PATCH 3/5] tty: serial: qcom_geni_serial: Use OPP API to set clk/perf state Date: Mon, 28 Jan 2019 17:55:45 -0800 Message-Id: <20190129015547.213276-4-swboyd@chromium.org> X-Mailer: git-send-email 2.20.1.495.gaa96b0ce6b-goog In-Reply-To: <20190129015547.213276-1-swboyd@chromium.org> References: <20190129015547.213276-1-swboyd@chromium.org> MIME-Version: 1.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rajendra Nayak geni serial needs to express a perforamnce state requirement on CX depending on the frequency of the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. Signed-off-by: Rajendra Nayak Signed-off-by: Stephen Boyd --- drivers/tty/serial/qcom_geni_serial.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index a72d6d9fb983..dca8f6845463 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -119,6 +120,7 @@ struct qcom_geni_serial_port { bool brk; unsigned int tx_remaining; + struct device *dev; }; static const struct uart_ops qcom_geni_console_pops; @@ -1028,7 +1030,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, goto out_restart_rx; uport->uartclk = clk_rate; - clk_set_rate(port->se.clk, clk_rate); + dev_pm_opp_set_rate(port->dev, clk_rate); ser_clk_cfg = SER_CLK_EN; ser_clk_cfg |= clk_div << CLK_DIV_SHFT; @@ -1265,8 +1267,10 @@ static void qcom_geni_serial_pm(struct uart_port *uport, if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) geni_se_resources_on(&port->se); else if (new_state == UART_PM_STATE_OFF && - old_state == UART_PM_STATE_ON) + old_state == UART_PM_STATE_ON) { + dev_pm_opp_set_rate(port->dev, 0); geni_se_resources_off(&port->se); + } } static const struct uart_ops qcom_geni_console_pops = { @@ -1332,6 +1336,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Invalid line %d\n", line); return PTR_ERR(port); } + port->dev = &pdev->dev; uport = &port->uport; /* Don't allow 2 drivers to access the same port */ @@ -1353,6 +1358,12 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) return -EINVAL; uport->mapbase = res->start; + ret = dev_pm_opp_of_add_table(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "failed to init OPP table: %d\n", ret); + return ret; + } + port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;