| Message ID | 20190204100910.26701-9-tudor.ambarus@microchip.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | spi: atmel-quadspi: introduce sam9x60 qspi controller | expand |
On Mon, 4 Feb 2019 10:09:53 +0000 <Tudor.Ambarus@microchip.com> wrote: > From: Tudor Ambarus <tudor.ambarus@microchip.com> > > Split the TFRTYP_TRSFR_ bitfields in 2: one bit encoding the > mem/reg transfer type and one bit encoding the direction of > the transfer (read/write). > > Remove NOP when setting read transfer type. Remove useless > setting of write transfer type when > op->data.dir == SPI_MEM_DATA_IN && !op->data.nbytes. > > QSPI_IFR_TFRTYP_TRSFR_WRITE is specific just to sama5d2 qspi, > rename it to QSPI_IFR_SAMA5D2_WRITE_TRSFR. > > Suggested-by: Boris Brezillon <bbrezillon@kernel.org> > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> > --- > v4: introduce QSPI_IFR_TFRTYP_MEM, reword commit > v3: new patch > > drivers/spi/atmel-quadspi.c | 13 ++++--------- > 1 file changed, 4 insertions(+), 9 deletions(-) > > diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c > index ce4f8a648f45..19a3980775ad 100644 > --- a/drivers/spi/atmel-quadspi.c > +++ b/drivers/spi/atmel-quadspi.c > @@ -113,11 +113,8 @@ > #define QSPI_IFR_OPTL_4BIT (2 << 8) > #define QSPI_IFR_OPTL_8BIT (3 << 8) > #define QSPI_IFR_ADDRL BIT(10) > -#define QSPI_IFR_TFRTYP_MASK GENMASK(13, 12) > -#define QSPI_IFR_TFRTYP_TRSFR_READ (0 << 12) > -#define QSPI_IFR_TFRTYP_TRSFR_READ_MEM (1 << 12) > -#define QSPI_IFR_TFRTYP_TRSFR_WRITE (2 << 12) > -#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEM (3 << 13) > +#define QSPI_IFR_TFRTYP_MEM BIT(12) > +#define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13) > #define QSPI_IFR_CRM BIT(14) > #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16) > #define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK) > @@ -275,10 +272,8 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) > if (op->data.nbytes) > ifr |= QSPI_IFR_DATAEN; > > - if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) > - ifr |= QSPI_IFR_TFRTYP_TRSFR_READ; > - else > - ifr |= QSPI_IFR_TFRTYP_TRSFR_WRITE; > + if (op->data.dir == SPI_MEM_DATA_OUT) > + ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR; > > /* Clear pending interrupts */ > (void)readl_relaxed(aq->regs + QSPI_SR);
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index ce4f8a648f45..19a3980775ad 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -113,11 +113,8 @@ #define QSPI_IFR_OPTL_4BIT (2 << 8) #define QSPI_IFR_OPTL_8BIT (3 << 8) #define QSPI_IFR_ADDRL BIT(10) -#define QSPI_IFR_TFRTYP_MASK GENMASK(13, 12) -#define QSPI_IFR_TFRTYP_TRSFR_READ (0 << 12) -#define QSPI_IFR_TFRTYP_TRSFR_READ_MEM (1 << 12) -#define QSPI_IFR_TFRTYP_TRSFR_WRITE (2 << 12) -#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEM (3 << 13) +#define QSPI_IFR_TFRTYP_MEM BIT(12) +#define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13) #define QSPI_IFR_CRM BIT(14) #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16) #define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK) @@ -275,10 +272,8 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) if (op->data.nbytes) ifr |= QSPI_IFR_DATAEN; - if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) - ifr |= QSPI_IFR_TFRTYP_TRSFR_READ; - else - ifr |= QSPI_IFR_TFRTYP_TRSFR_WRITE; + if (op->data.dir == SPI_MEM_DATA_OUT) + ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR; /* Clear pending interrupts */ (void)readl_relaxed(aq->regs + QSPI_SR);