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Received: from nwd2mta1.analog.com (137.71.25.55) by SN1NAM02FT060.mail.protection.outlook.com (10.152.72.192) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.1987.11 via Frontend Transport; Tue, 25 Jun 2019 13:13:47 +0000 Received: from NWD2HUBCAS7.ad.analog.com (nwd2hubcas7.ad.analog.com [10.64.69.107]) by nwd2mta1.analog.com (8.13.8/8.13.8) with ESMTP id x5PDDk0V008727 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=OK); Tue, 25 Jun 2019 06:13:46 -0700 Received: from saturn.ad.analog.com (10.48.65.145) by NWD2HUBCAS7.ad.analog.com (10.64.69.107) with Microsoft SMTP Server id 14.3.408.0; Tue, 25 Jun 2019 09:13:46 -0400 From: Alexandru Ardelean To: , , , CC: Alexandru Ardelean , Michael Hennerich Subject: [PATCH 2/5] drivers: spi: core: Add optional stall delay between cs_change transfers Date: Tue, 25 Jun 2019 16:13:25 +0300 Message-ID: <20190625131328.11883-2-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190625131328.11883-1-alexandru.ardelean@analog.com> References: <20190625131328.11883-1-alexandru.ardelean@analog.com> MIME-Version: 1.0 X-ADIRoutedOnPrem: True X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:137.71.25.55;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(136003)(346002)(396003)(39860400002)(376002)(2980300002)(199004)(189003)(51416003)(2201001)(186003)(76176011)(106002)(7696005)(54906003)(450100002)(336012)(14444005)(86362001)(48376002)(50466002)(305945005)(110136005)(5660300002)(77096007)(26005)(446003)(36756003)(8676002)(11346002)(356004)(316002)(476003)(4326008)(426003)(478600001)(2616005)(2906002)(1076003)(8936002)(6666004)(47776003)(70206006)(70586007)(2870700001)(107886003)(44832011)(50226002)(246002)(7636002)(486006)(126002);DIR:OUT;SFP:1101;SCL:1;SRVR:MWHSPR01MB320;H:nwd2mta1.analog.com;FPR:;SPF:Pass;LANG:en;PTR:nwd2mail10.analog.com;A:1;MX:1; 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The default value of 10us is not enough. This change makes the delay configurable for when the next CS change goes active. Signed-off-by: Michael Hennerich Signed-off-by: Alexandru Ardelean --- drivers/spi/spi.c | 3 ++- include/linux/spi/spi.h | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 5e75944ad5d1..739de0118ee1 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -1163,7 +1163,8 @@ static int spi_transfer_one_message(struct spi_controller *ctlr, keep_cs = true; } else { spi_set_cs(msg->spi, false); - udelay(10); + udelay(xfer->cs_change_stall_delay_us ? + xfer->cs_change_stall_delay_us : 10); spi_set_cs(msg->spi, true); } } diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 053abd22ad31..d23add3b4790 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -734,6 +734,8 @@ extern void spi_res_release(struct spi_controller *ctlr, * transfer. If 0 the default (from @spi_device) is used. * @bits_per_word: select a bits_per_word other than the device default * for this transfer. If 0 the default (from @spi_device) is used. + * @cs_change_stall_delay_us: microseconds to delay between cs_change + * transfers. * @cs_change: affects chipselect after this transfer completes * @delay_usecs: microseconds to delay after this transfer before * (optionally) changing the chipselect status, then starting @@ -823,6 +825,7 @@ struct spi_transfer { #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */ u8 bits_per_word; u8 word_delay_usecs; + u8 cs_change_stall_delay_us; u16 delay_usecs; u32 speed_hz; u16 word_delay;