| Message ID | 20191024110757.25820-2-alvaro.gamez@hazent.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | e3354b17b4ac10ad2c23e244444ab38927a69ee9 |
| Headers | show |
| Series | spi: xilinx: add description of new property xlnx,num-transfer-bits | expand |
On Thu, Oct 24, 2019 at 01:07:55PM +0200, Alvaro Gamez Machado wrote: > This property is used to set the number of bits per transfer (bits_per_word). > > Xilinx' IP core allows either 8, 16 or 32, and is non changeable on runtime, > only when instantiating the core. When sending a patch series you should number the patches within the series - if you use git format-patch to generate the series it'll do that for you. Instead of [PATCH] it should say [PATCH x/y].
diff --git a/Documentation/devicetree/bindings/spi/spi-xilinx.txt b/Documentation/devicetree/bindings/spi/spi-xilinx.txt index dc924a5f71db..5f4ed3e5c994 100644 --- a/Documentation/devicetree/bindings/spi/spi-xilinx.txt +++ b/Documentation/devicetree/bindings/spi/spi-xilinx.txt @@ -8,7 +8,8 @@ Required properties: number. Optional properties: -- xlnx,num-ss-bits : Number of chip selects used. +- xlnx,num-ss-bits : Number of chip selects used. +- xlnx,num-transfer-bits : Number of bits per transfer. This will be 8 if not specified Example: axi_quad_spi@41e00000 { @@ -17,5 +18,6 @@ Example: interrupts = <0 31 1>; reg = <0x41e00000 0x10000>; xlnx,num-ss-bits = <0x1>; + xlnx,num-transfer-bits = <32>; };
This property is used to set the number of bits per transfer (bits_per_word). Xilinx' IP core allows either 8, 16 or 32, and is non changeable on runtime, only when instantiating the core. Signed-off-by: Alvaro Gamez Machado <alvaro.gamez@hazent.com> --- Documentation/devicetree/bindings/spi/spi-xilinx.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)