From patchwork Fri Nov 8 10:59:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 11234555 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DDECB1747 for ; Fri, 8 Nov 2019 10:59:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C6C6A218AE for ; Fri, 8 Nov 2019 10:59:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730614AbfKHK72 (ORCPT ); Fri, 8 Nov 2019 05:59:28 -0500 Received: from relay4-d.mail.gandi.net ([217.70.183.196]:38893 "EHLO relay4-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727573AbfKHK72 (ORCPT ); Fri, 8 Nov 2019 05:59:28 -0500 X-Originating-IP: 86.206.246.123 Received: from localhost.localdomain (lfbn-tou-1-421-123.w86-206.abo.wanadoo.fr [86.206.246.123]) (Authenticated sender: miquel.raynal@bootlin.com) by relay4-d.mail.gandi.net (Postfix) with ESMTPSA id 3B8F2E001A; Fri, 8 Nov 2019 10:59:26 +0000 (UTC) From: Miquel Raynal To: Mark Brown , Michal Simek , Naga Sureshkumar Relli Cc: Thomas Petazzoni , , , Tudor Ambarus , Miquel Raynal Subject: [PATCH 3/7] spi: zynq-qspi: Keep the bitfields naming consistent Date: Fri, 8 Nov 2019 11:59:16 +0100 Message-Id: <20191108105920.19014-4-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191108105920.19014-1-miquel.raynal@bootlin.com> References: <20191108105920.19014-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Most of the bits/bitfields #define'd in this driver are composed with: 1/ the driver prefix 2/ the name of the register they apply to Keep the naming consistent by applying this rule to the CONFIG register internals. These definitions will be used in a following change set. Signed-off-by: Miquel Raynal --- drivers/spi/spi-zynq-qspi.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c index 399c3ca33abb..11a484aa3186 100644 --- a/drivers/spi/spi-zynq-qspi.c +++ b/drivers/spi/spi-zynq-qspi.c @@ -61,9 +61,9 @@ * These are the values used in the calculation of baud rate divisor and * setting the slave select. */ -#define ZYNQ_QSPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */ -#define ZYNQ_QSPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */ -#define ZYNQ_QSPI_SS_SHIFT 10 /* Slave Select field shift in CR */ +#define ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */ +#define ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift */ +#define ZYNQ_QSPI_CONFIG_PCS 10 /* Peripheral Chip Select */ /* * QSPI Interrupt Registers bit Masks @@ -318,7 +318,7 @@ static void zynq_qspi_chipselect(struct spi_device *spi, bool assert) /* Select the slave */ config_reg &= ~ZYNQ_QSPI_CONFIG_SSCTRL_MASK; config_reg |= (((~(BIT(spi->chip_select))) << - ZYNQ_QSPI_SS_SHIFT) & + ZYNQ_QSPI_CONFIG_PCS) & ZYNQ_QSPI_CONFIG_SSCTRL_MASK); } else { config_reg |= ZYNQ_QSPI_CONFIG_SSCTRL_MASK; @@ -349,7 +349,7 @@ static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi) u32 config_reg, baud_rate_val = 0; /* Set the clock frequency */ - while ((baud_rate_val < ZYNQ_QSPI_BAUD_DIV_MAX) && + while ((baud_rate_val < ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX) && (clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) > spi->max_speed_hz) baud_rate_val++; @@ -364,7 +364,7 @@ static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi) config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK; config_reg &= ~ZYNQ_QSPI_CONFIG_BDRATE_MASK; - config_reg |= (baud_rate_val << ZYNQ_QSPI_BAUD_DIV_SHIFT); + config_reg |= (baud_rate_val << ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT); zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg); return 0;