From patchwork Fri May 8 18:54:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 11537463 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0F8FF14B4 for ; Fri, 8 May 2020 18:55:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EB68A21974 for ; Fri, 8 May 2020 18:55:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="vkE5/F26" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726811AbgEHSz2 (ORCPT ); Fri, 8 May 2020 14:55:28 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:56330 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726767AbgEHSz2 (ORCPT ); Fri, 8 May 2020 14:55:28 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 048Isok9041770; Fri, 8 May 2020 13:54:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1588964090; bh=5+AXR5SrX42+acbZCSDv1ai6NbQTlDljtTfawPkCDCs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vkE5/F26rfmlS1cg/GH+baBHHaCOxfMa2hkB25bNA3KCHpS1JPMBXFh/cfWcd/2t/ T9dB0cyVjHCERe2f6iKx+vAshUlnCB1+OXzZw/8H3ce9isq2uznYSdyjwh/qi2zGMG gnGUjde9LNuKCUWHKVq3Upf2EfnB38CPApA+toE0= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 048Iso5A013748 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 8 May 2020 13:54:50 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 8 May 2020 13:54:50 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 8 May 2020 13:54:50 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 048IsGpY077355; Fri, 8 May 2020 13:54:46 -0500 From: Vignesh Raghavendra To: Tudor Ambarus , Mark Brown CC: Vignesh Raghavendra , Boris Brezillon , Ramuthevar Vadivel Murugan , , , , , , Subject: [PATCH 6/6] spi: Move cadence-quadspi driver to drivers/spi/ Date: Sat, 9 May 2020 00:24:11 +0530 Message-ID: <20200508185411.487-7-vigneshr@ti.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200508185411.487-1-vigneshr@ti.com> References: <20200508185411.487-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ramuthevar Vadivel Murugan Now that cadence-quadspi has been converted to use spi-mem framework, move it under drivers/spi/ Update license header to match SPI subsystem style Signed-off-by: Ramuthevar Vadivel Murugan Signed-off-by: Vignesh Raghavendra --- drivers/mtd/spi-nor/controllers/Kconfig | 11 ----------- drivers/mtd/spi-nor/controllers/Makefile | 1 - drivers/spi/Kconfig | 11 +++++++++++ drivers/spi/Makefile | 1 + .../spi-cadence-quadspi.c} | 14 +++++++------- 5 files changed, 19 insertions(+), 19 deletions(-) rename drivers/{mtd/spi-nor/controllers/cadence-quadspi.c => spi/spi-cadence-quadspi.c} (99%) diff --git a/drivers/mtd/spi-nor/controllers/Kconfig b/drivers/mtd/spi-nor/controllers/Kconfig index 10b86660b821..95fcd4b435be 100644 --- a/drivers/mtd/spi-nor/controllers/Kconfig +++ b/drivers/mtd/spi-nor/controllers/Kconfig @@ -9,17 +9,6 @@ config SPI_ASPEED_SMC and support for the SPI flash memory controller (SPI) for the host firmware. The implementation only supports SPI NOR. -config SPI_CADENCE_QUADSPI - tristate "Cadence Quad SPI controller" - depends on OF && (ARM || ARM64 || COMPILE_TEST) - help - Enable support for the Cadence Quad SPI Flash controller. - - Cadence QSPI is a specialized controller for connecting an SPI - Flash over 1/2/4-bit wide bus. Enable this option if you have a - device with a Cadence QSPI controller and want to access the - Flash as an MTD device. - config SPI_HISI_SFC tristate "Hisilicon FMC SPI-NOR Flash Controller(SFC)" depends on ARCH_HISI || COMPILE_TEST diff --git a/drivers/mtd/spi-nor/controllers/Makefile b/drivers/mtd/spi-nor/controllers/Makefile index 46e6fbe586e3..e7abba491d98 100644 --- a/drivers/mtd/spi-nor/controllers/Makefile +++ b/drivers/mtd/spi-nor/controllers/Makefile @@ -1,6 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o -obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 17e7e4afc0fc..15f308571163 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -200,6 +200,17 @@ config SPI_CADENCE This selects the Cadence SPI controller master driver used by Xilinx Zynq and ZynqMP. +config SPI_CADENCE_QUADSPI + tristate "Cadence Quad SPI controller" + depends on OF && (ARM || ARM64 || COMPILE_TEST) + help + Enable support for the Cadence Quad SPI Flash controller. + + Cadence QSPI is a specialized controller for connecting an SPI + Flash over 1/2/4-bit wide bus. Enable this option if you have a + device with a Cadence QSPI controller and want to access the + Flash as an MTD device. + config SPI_CLPS711X tristate "CLPS711X host SPI controller" depends on ARCH_CLPS711X || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 889368f4ad53..f03834d1d312 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_SPI_BCM_QSPI) += spi-iproc-qspi.o spi-brcmstb-qspi.o spi-bcm-qspi. obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o obj-$(CONFIG_SPI_CADENCE) += spi-cadence.o +obj-$(CONFIG_SPI_CADENCE_QUADSPI) += spi-cadence-quadspi.o obj-$(CONFIG_SPI_CLPS711X) += spi-clps711x.o obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o diff --git a/drivers/mtd/spi-nor/controllers/cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c similarity index 99% rename from drivers/mtd/spi-nor/controllers/cadence-quadspi.c rename to drivers/spi/spi-cadence-quadspi.c index d788692efc55..de009e44f2aa 100644 --- a/drivers/mtd/spi-nor/controllers/cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0-only -/* - * Driver for Cadence QSPI Controller - * - * Copyright Altera Corporation (C) 2012-2014. All rights reserved. - * Copyright Intel Corporation (C) 2019-2020. All rights reserved. - * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com - */ +// +// Driver for Cadence QSPI Controller +// +// Copyright Altera Corporation (C) 2012-2014. All rights reserved. +// Copyright Intel Corporation (C) 2019-2020. All rights reserved. +// Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com + #include #include #include